Fix Sphinx warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193493 91177308-0d34-0410-b5e6-96231b3b80d8
Update to current output.
PR14039

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193494 91177308-0d34-0410-b5e6-96231b3b80d8
A small grammar-os fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193496 91177308-0d34-0410-b5e6-96231b3b80d8
AVX-512: PMIN/PMAX intrinsics and patterns
Patch by Cameron McInally <cameron.mcinally@nyu.edu>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193497 91177308-0d34-0410-b5e6-96231b3b80d8
MCJIT-remote: __main should be resolved in child context.

  - Mark tests as XFAIL:cygming in test/ExecutionEngine/MCJIT/remote.
    Rather to suppress them, I'd like to leave them running as XFAIL.
  - Revert r193472. RecordMemoryManager no longer resolves __main on cygming.

There are a couple of issues.

  - X86 Codegen emits "call __main" in @main for targeting cygming.
    It is useless in JIT. FYI, tests are passing when emitting __main is disabled.
  - Current remote JIT does not resolve any symbols in child context.

FIXME: __main should be disabled, or remote JIT should resolve __main.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193498 91177308-0d34-0410-b5e6-96231b3b80d8
Hexagon: Remove global state.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193499 91177308-0d34-0410-b5e6-96231b3b80d8
NVPTX: Remove unused globals.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193500 91177308-0d34-0410-b5e6-96231b3b80d8
Clarify the comment about BSD versions in r193465

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193508 91177308-0d34-0410-b5e6-96231b3b80d8
Make first substantial checkin of my port of ARM constant islands code to Mips.
Before I just ported the shell of the pass. I've tried to keep everything
nearly identical to the ARM version. I think it will be very easy to eventually
merge these two and create a new more general pass that other targets can
use. I have some improvements I would like to make to allow pools to 
be shared across functions and some other things. When I'm all done we
can think about making a more general pass. More to be ported but the
basic mechanism works now almost as good as gcc mips16.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193509 91177308-0d34-0410-b5e6-96231b3b80d8
Target/R600: Un-tab-ify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193510 91177308-0d34-0410-b5e6-96231b3b80d8
Prune trailing linefeeds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193511 91177308-0d34-0410-b5e6-96231b3b80d8
Prune utf8 chars in comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193512 91177308-0d34-0410-b5e6-96231b3b80d8
SCEV: Make the final add of an inbounds GEP nuw if we know that the index is positive.

We can't do this for the general case as saying a GEP with a negative index
doesn't have unsigned wrap isn't valid for negative indices.
  %gep = getelementptr inbounds i32* %p, i64 -1

But an inbounds GEP cannot run past the end of address space. So we check for
the very common case of a positive index and make GEPs derived from that NUW.
Together with Andy's recent non-unit stride work this lets us analyze loops
like

  void foo3(int *a, int *b) {
    for (; a < b; a++) {}
  }

PR12375, PR12376.

Differential Revision: http://llvm-reviews.chandlerc.com/D2033

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193514 91177308-0d34-0410-b5e6-96231b3b80d8
lit: multiprocessing platform fix attempt

The error raised by Python varies by platform(!), so let's just catch any
exception and fall back.

Thanks to Sylvestre Ledru for noticing this on a Debian / Python 2.7 system
running code coverage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193516 91177308-0d34-0410-b5e6-96231b3b80d8
Keep TBAA info when rewriting SelectionDAG loads and stores

Most SelectionDAG code drops the TBAA info when creating a new form of a
load and store (e.g. during legalization, or when converting a plain
load to an extending one).  This patch tries to catch all cases where
the TBAA information can legitimately be carried over.

The patch adds alternative forms of getLoad() and getExtLoad() that take
a MachineMemOperand instead of individual fields.  (The corresponding
getTruncStore() already exists.)  The idea is to use the MachineMemOperand
forms when all fields are carried over (size, pointer info, isVolatile,
isNonTemporal, alignment and TBAA info).  If some adjustment is being
made, e.g. to narrow the load, then we still pass the individual fields
but also pass the TBAA info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193517 91177308-0d34-0410-b5e6-96231b3b80d8
[DAGCombiner] Respect volatility when checking for aliases

Making useAA() default to true for SystemZ showed that the combiner alias
analysis wasn't handling volatile accesses.  This hit many of the SystemZ
tests, but I arbitrarily picked one for the purpose of this patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193518 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Set usaAA to true

useAA significantly improves the handling of vector code that has TBAA
information attached.  It also helps other cases, as shown by the testsuite
changes here.  The only real downside I've seen is that it interferes with
MergeConsecutiveStores.  The problem is that that optimization works top
down, starting at the first store in the chain, and looks for cases where
the chain result is only used by a single related store.  These related
stores don't alias, so useAA will have rewritten all the later stores to
use a different chain input (typically the same one as the first store).

I think the advantages outweigh the disadvantages though, so for now I've
just disabled alias analysis for the unaligned-01.ll test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193521 91177308-0d34-0410-b5e6-96231b3b80d8
simplify ConstantRange::getSetSize()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193523 91177308-0d34-0410-b5e6-96231b3b80d8
[arm] Implement eabi_attribute, cpu, and fpu directives.

This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.

To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.

Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.

This commit changes the test cases:

* Several .eabi_attribute directives in
  2010-09-29-mc-asm-header-test.ll are removed because the .fpu
  directive already cover the functionality.

* In the Cortex-A15 test case, the value for
  Tag_Advanced_SIMD_arch has be changed from 1 to 2,
  which is more precise.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen: Refactor AsmWriterEmitter to keep AsmWriterInsts.

These used to be referenced by the CGI->AWI map (in AsmWriterEmitter), but
stored in a vector local to EmitPrintInstruction. Move the vector to
AsmWriterEmitter too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193525 91177308-0d34-0410-b5e6-96231b3b80d8