Verilog utils

Main motivator for this pull-request is a 'bug' in Xilinx ISE versions < 14.1,
where  $clog2 would not evaluate correctly.
It adds a new core with convenient functions gathered in one place,
and it also makes wb_intercon take it into use.
The changes has been tested against verilator, icarus, Xilinx ISE and altera quartus.