[ARM] emulate_arm: Treate cache preload instructions as NOPs

The latest 3.16 kernel used PLDW instruction in spinlock implementation.

Unfortunately, on latest QEMU this instruction give undefined exception
for Cortex-A8 (i.e. UP ARMv7 host) which is very strange because the
ARMv7 architecture reference manual does not tell that PLDW instructions
are only available fo ARMv7MP.

Using this patch, we treate all preload instructions as NOPs in
ARM instruction emulation. This way if preload instruction trap
in Xvisor then we simply/safely ignore it.

Signed-off-by: Anup Patel <anup@brainfault.org>