[X86] Improved lowering of packed vector shifts to vpsllq/vpsrlq.

SSE2/AVX non-constant packed shift instructions only use the lower 64-bit of
the shift count.

This patch teaches function 'getTargetVShiftNode' how to deal with shifts
where the shift count node is of type MVT::i64.

Before this patch, function 'getTargetVShiftNode' only knew how to deal with
shift count nodes of type MVT::i32. This forced the backend to wrongly
truncate the shift count to MVT::i32, and then zero-extend it back to MVT::i64.