hdl/modules/*: add SLAC modifications
hdl/*/wb_position_calc/*: change swithing window to Tukey 1.0

This is for testing the RFFE_v1, with long switch dead-time
hdl/modules/*/generated/virtex6/*: Change FOFB decim factor

The FOFB rate now has a decimation factor
of 1000 instead of 1112. In this way, the
BPM numerology gets much easier
hdl/modules/*/generated/virtex6/*: change LUT filename

WARNING! This approach is not good as this file
is automatically generated by Sysgen!
hdl/modules/*/generated/artix7/*: Change FOFB decim factor

The FOFB rate now has a decimation factor
of 1000 instead of 1112. In this way, the
BPM numerology gets much easier
hdl/modules/*/generated/artix7/*: change LUT filename

WARNING! This approach is not good as this file
is automatically generated by Sysgen!
hdl/modules/sw_windowing/*: add window fucntion compatible with octave

The previous windowgen funcion had some particularities
regarding MATLAB. Now, a new function was created compatible
with OCTAVE
hdl/modules/sw_windowing/*: add 500-point length window

This window is used for a switching frequency of
1000 rate in relation to the ADC clock
hdl/modules/wb_position_calc/*: change Window LUT to 500-point
hdl/modules/sw_windowing/*: add 500-point, tukey 0.2, length window

This window is used for a switching frequency of
1000 rate in relation to the ADC clock
hdl/modules/wb_position_calc/*: change Window LUT to 500-point, Tukey 0.2
hdl/modules/dsp_cores_pkg.vhd: (1/3) adhere to the new generated components

As we generated a DSP chain with 1000 ratio
instead of 1112, the CE nets change its names.
Hence, we need to change them in all of the
modules that use them
hdl/modules/dsp_cores_pkg.vhd: (1/3) adhere to the new generated components

As we generated a DSP chain with 1000 ratio
instead of 1112, the CE nets change its names.
Hence, we need to change them in all of the
modules that use them
hdl/modules/position_calc/*: (2/3) adhere to the new generated components

As we generated a DSP chain with 1000 ratio
instead of 1112, the CE nets change its names.
Hence, we need to change them in all of the
modules that use them
hdl/modules/wb_position_calc/*: (3/3) adhere to the new generated components

As we generated a DSP chain with 1000 ratio
instead of 1112, the CE nets change its names.
Hence, we need to change them in all of the
modules that use them
hdl/modules/position_calc/*: (2/3) adhere to the new generated components

As we generated a DSP chain with 1000 ratio
instead of 1112, the CE nets change its names.
Hence, we need to change them in all of the
modules that use them
hdl/modules/wb_position_calc/*: (3/3) adhere to the new generated components

As we generated a DSP chain with 1000 ratio
instead of 1112, the CE nets change its names.
Hence, we need to change them in all of the
modules that use them
hdl/modules/*: add deswitching clk to position_calc_core module
hdl/modules/wb_un_cross/wbgen/*: (1/5) update wbgen files

Add switching clock output enable. This effectively
starts the switch counter from 0 to the max value.
This is necessary as the RFFE controller needs to
be in a known state before the first switching clock
edge.

This is accomplished by disabling the switching clock,
commanding the RFFE controller to the direct switch state
and then enabling the switching clock
hdl/modules/wb_un_cross/*: (2/5) add switching clock enable input

Use switching clock enable in the clock generation logic