msm: mdss: Move bus scale table implementation to device-tree

Bus scale table is chip-set dependent where number of paths per
bandwidth use-case can differ chip-set to chip-set. Current
implementation has a static table where it supports only one path per
use-case. Expand MDSS bus scaling implementation to accommodate
chip-sets where more than one path per use-case, i.e. apq8084, is
possible and move table initialization to device-tree so that every
chip-set configures its own table.

Change-Id: Ia6f76654d129fe0ec1a7124aa87b16f96167fe84
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Do not program DSI PLL registers from DSI controller

MDSS DSI driver currently programs certain DSI PLL registers as
part of the DSI PHY off sequence. This is incorrect and could
lead to some unexpected errors such as DSI PLL getting turned off
while the branch clocks are still on. Fix this by removing all
such register programming.

Change-Id: Ie1e88cd18de6b8ef8804f7a2b34b8b8282166c96
CRs-Fixed: 509801
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: add a separate register region for DSI PHY

The DSI PHY register offset from the controller base is
different for different targets. So, add a separate register
region for DSI PHY in the device tree. This register base and
offset will be used to access the DSI PHY registers. Also
change the register offsets which are dependent on the
controller base address.

Change-Id: Ie1d08950f3c8c8801908a1b3cf7db46a44b4e8c3
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: cleanup dsi clock handling

Currently the DSI driver uses a two level reference counting for
the clocks used by the driver so as to ensure that the clocks are
correctly configured for dual-dsi use cases. However, this is not
necessary as the same can be achieved by using a single reference
count. Clean up the code to remove the sub-level ref counts and
add necessary error handling.

Change-Id: I6f1c1bfe83322dc0e1da3d757b6ca88cd629663e
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Add support to selectively control bus and link clocks

DSI driver needs two different types of clocks for normal
operation - bus clocks and link clocks. The clock control function
enables/disables both these set of clocks together. However,
under certain circumstances, it is required to control just the
link clocks or the bus clocks. To support this, add separate
ref counts for link and bus clocks and modify the clock control
function to selectively control these clocks.

Change-Id: I25312131fc737b56dc15f4edf5e55a5824dad855
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Turn on DSI link clocks after exiting ULPS

DSI branch clocks should only be enabled after removing the DSI clamps
when exiting the Ultra Low Power State (ULPS). If this is not enforced,
then the RCG for these clocks may not get turned on correctly which
may eventually lead to some display corruption. Fix this by
appropriately modifying ULPS exit sequence.

Change-Id: I5109dd140f8921256f95eb479dd33a73615d489f
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: refactor pipe retrieval and ref count logic

Allow only retrieval of pipes that are on particular framebuffer device
used list. This ensures that pipe is not modified from a different fb
device node and cause potential issues.

Also, modify the ref count logic to use kref and ensure pipe is freed
only while holding mutex in case there could be race condition that
pipe is allocated while being freed.

Change-Id: I626323b5df981a7ed1e03196126cd4376b5ba6a6
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Signed-off-by: Anusha Koduru <kanusha@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Add BTA status check API in DSI controller

Add Bus-Turn-Around (BTA) status check API in DSI
controller to check if it is alive or not. Subscriber
of this API should send relevant notification to user
space for correct action. Update fb driver and cmd
interface to support the BTA failure scenario.

Change-Id: Ic78379b31a48278282182fdba6ba7b2e6f9c26d5
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Fix clk warnings for esc clk with dual-dsi panels

In current implementation if dual-dsi panel's continuous splash screen
feature is enabled then feature flag is disabled only for master and
not for secondary panel. This leads to clk prepare without clk set rate.
For esc clk this leads to clk warning back-trace in the logs. For other
clocks, if clk rate changes between suspend/resume then it will lead to
rate incorrect programming and unknown behaviour. Fix this by disabling
secondary panel's feature flag.

Change-Id: I09fd3968c4eecc97a9f07e2c731e6ccce8036119
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Check ctl in mdss_mdp_mixer_get before using

Put NULL check for ctl before using in mdss_mdp_mixer_get.

Change-Id: Ia1bc035df46c9e237c244623e61a6802cf0d9110
Signed-off-by: Pawan Kumar <pavaku@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: fix DCS backlight control when broadcast mode is enabled

When broadcast mode is enabled, we trigger DCS commands when cmds_tx
is done on controller 1. This call is missing in the path of
backlight control using DCS commands. Add this call to fix DCS
backlight issues for broadcast mode.

Change-Id: I18193375e180a42fb1db42fb1d52a976b660ae1c
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
mdss: display: add spin_lock to mdss_disable_irq_nosync()

Add spin_lock to mdss_lock inside mdss_disable_irq_nosync
to avoid race condition which can cause mdss_irq to be disabled
while irq_mask bits are still set.

CRs-Fixed: 624806
Change-Id: I44074a057dff49dfc7a4d2829f3c4e599dca4a69
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: dsi: check ULPS state only for active lanes

It is possible that for certain panels, not all four data lanes are
active. After configuring the lanes to Ultra Low Power State (ULPS),
only check the status of the active lanes since the lanes that are not
used will never enter ULPS.

Change-Id: I0da358f2bd24d4472cfccb6cca9ca8b26ffa8226
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Add support for sending panel off commands in LP mode

Add support to send panel Off commands for video mode during LP
mode. This is needed to support few video mode panels which have
BLLP power mode set to HS and it is not possible to send Off
commands when pixel data is active. Hence, make changes to send
panel Off commands for such panels in LP mode after TG is
turned off.

Change-Id: I1c9f3fd1e9e052b5254cfdcf58cd974dfbe3dc8e
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: dsi: fix error handling when clk enable fails

When clock enable fails, the error handling logic should ensure
to remove the reference counts for the master controller clocks only
if the master controller is valid. Add the necessary checks to ensure
this so as to avoid any null pointer dereferences.

Change-Id: If2779c4febe19d882a8247872de6fac94f5b0ded
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: disable irq to enforce mutex within dsi_event_thread

Mdp spin lock is used in dsi_event_thread and in irq context.
Disable irq while holding spinlock to avoid context switching
into irq context and cause spinlock recursion

CRs-fixed: 652850
Change-Id: I4bd8cadb1f5d83acc7e866344b7585e7944e08ac
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Clear the previous state of pipe during SOLID_FILL

Clear the previous state of pipe when it is being used in SOLID_FILL
operation to prevent wrong register configuration. For ex: Use case
when DMA pipe was used in BLOCK mode in previous frame, then it is
being used in LINE mode for SOLID_FILL operation in current frame.

CRs-Fixed: 655993
Change-Id: I0ed257276428b96c10a92457a16df4dfdc42c1f8
Signed-off-by: Sushil Chauhan <sushilchauhan@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
futex: move user address verification up to common code

When debugging the read-only hugepage case, I was confused by the fact
that get_futex_key() did an access_ok() only for the non-shared futex
case, since the user address checking really isn't in any way specific
to the private key handling.

Now, it turns out that the shared key handling does effectively do the
equivalent checks inside get_user_pages_fast() (it doesn't actually
check the address range on x86, but does check the page protections for
being a user page).  So it wasn't actually a bug, but the fact that we
treat the address differently for private and shared futexes threw me
for a loop.

Just move the check up, so that it gets done for both cases.  Also, use
the 'rw' parameter for the type, even if it doesn't actually matter any
more (it's a historical artifact of the old racy i386 "page faults from
kernel space don't check write protections").

Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
futexes: Clean up various details

- Remove unnecessary head variables.
- Delete unused parameter in queue_unlock().

Reviewed-by: Darren Hart <dvhart@linux.intel.com>
Reviewed-by: Peter Zijlstra <peterz@infradead.org>
Reviewed-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Jason Low <jason.low2@hp.com>
Signed-off-by: Davidlohr Bueso <davidlohr@hp.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Jeff Mahoney <jeffm@suse.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Scott Norton <scott.norton@hp.com>
Cc: Tom Vaden <tom.vaden@hp.com>
Cc: Aswin Chandramouleeswaran <aswin@hp.com>
Cc: Waiman Long <Waiman.Long@hp.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Link: http://lkml.kernel.org/r/1389569486-25487-2-git-send-email-davidlohr@hp.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
futexes: Increase hash table size for better performance

Currently, the futex global hash table suffers from its fixed,
smallish (for today's standards) size of 256 entries, as well as
its lack of NUMA awareness. Large systems, using many futexes,
can be prone to high amounts of collisions; where these futexes
hash to the same bucket and lead to extra contention on the same
hb->lock. Furthermore, cacheline bouncing is a reality when we
have multiple hb->locks residing on the same cacheline and
different futexes hash to adjacent buckets.

This patch keeps the current static size of 16 entries for small
systems, or otherwise, 256 * ncpus (or larger as we need to
round the number to a power of 2). Note that this number of CPUs
accounts for all CPUs that can ever be available in the system,
taking into consideration things like hotpluging. While we do
impose extra overhead at bootup by making the hash table larger,
this is a one time thing, and does not shadow the benefits of
this patch.

Furthermore, as suggested by tglx, by cache aligning the hash
buckets we can avoid access across cacheline boundaries and also
avoid massive cache line bouncing if multiple cpus are hammering
away at different hash buckets which happen to reside in the
same cache line.

Also, similar to other core kernel components (pid, dcache,
tcp), by using alloc_large_system_hash() we benefit from its
NUMA awareness and thus the table is distributed among the nodes
instead of in a single one.

For a custom microbenchmark that pounds on the uaddr hashing --
making the wait path fail at futex_wait_setup() returning
-EWOULDBLOCK for large amounts of futexes, we can see the
following benefits on a 80-core, 8-socket 1Tb server:

 +---------+--------------------+------------------------+-----------------------+-------------------------------+
 | threads | baseline (ops/sec) | aligned-only (ops/sec) | large table (ops/sec) | large table+aligned (ops/sec) |
 +---------+--------------------+------------------------+-----------------------+-------------------------------+
 |     512 |              32426 | 50531  (+55.8%)        | 255274  (+687.2%)     | 292553  (+802.2%)             |
 |     256 |              65360 | 99588  (+52.3%)        | 443563  (+578.6%)     | 508088  (+677.3%)             |
 |     128 |             125635 | 200075 (+59.2%)        | 742613  (+491.1%)     | 835452  (+564.9%)             |
 |      80 |             193559 | 323425 (+67.1%)        | 1028147 (+431.1%)     | 1130304 (+483.9%)             |
 |      64 |             247667 | 443740 (+79.1%)        | 997300  (+302.6%)     | 1145494 (+362.5%)             |
 |      32 |             628412 | 721401 (+14.7%)        | 965996  (+53.7%)      | 1122115 (+78.5%)              |
 +---------+--------------------+------------------------+-----------------------+-------------------------------+

Reviewed-by: Darren Hart <dvhart@linux.intel.com>
Reviewed-by: Peter Zijlstra <peterz@infradead.org>
Reviewed-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Reviewed-by: Waiman Long <Waiman.Long@hp.com>
Reviewed-and-tested-by: Jason Low <jason.low2@hp.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Davidlohr Bueso <davidlohr@hp.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Jeff Mahoney <jeffm@suse.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Scott Norton <scott.norton@hp.com>
Cc: Tom Vaden <tom.vaden@hp.com>
Cc: Aswin Chandramouleeswaran <aswin@hp.com>
Link: http://lkml.kernel.org/r/1389569486-25487-3-git-send-email-davidlohr@hp.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>