altera pcie: add sdb record for MSI slave interface
wishbone: add a timing cutter
crossbar: allow slaves with address=0 and !mask=0 --> they are unreachable

This makes it possible to connect a slave to the crossbar which is optimized
away by the synthesis tool. This is useful when some slaves attached to the
crossbar are optional.
sdb_crossbar: fix the meta-data ignore rule; disconnect the slave port
wishbone: sdb auto crossbar mapping support
Merge branch 'crossbar-improvements' into proposed_master

Include automatic crossbar layout and timing improvement clock cutter.
auto crossbar: appease modelsim
wishbone_pkg: bugfix for f_sdb_create_array
wb_irq_slave: added clear and enable registers
modules/wishbone: c_vuart_fifo_size exported as generic parameter

This change is necessary for network control/monitor tool in order to read the GUI command output.
The GUI command output can not be stored into a 1024 bytes fifo.
wb_crossbar: allow extra SDB records at the end of the layout
i2c-bridge: Updated bridge and slave modules

Bridge: Removed "redundant" SIM_WB_TRANSFER state.

Slave: Removed redundant ADDR_CHECK state and moved its code to
the ADDR state.

Also corrected a bug whereby the ack_i pin was not being checked within
the ADDR_ACK state. This was causing the FSM to advance even thogh the
slave was actually NACK-ing.

DOC: Updated documentation for both these modules

Signed-off-by: Theodor Stana <t.stana@cern.ch>
multiboot: Updated wbgen2 file for documentation

Also updated the rest of the documentation file to have a pretty
regmap.

Signed-off-by: Theodor Stana <t.stana@cern.ch>
switch-optimization: generic to disable virtex6 fifo utilization counting
fix almost_full threshold for Virtex6 FIFO

Xilinx defines almost full threshold not as the used words in the FIFO but as
number of available empty words (UG363 - Virtex 6 FPGA Memory Resources
inferred_async_fifo: Assigned full and almost full and empty outputs in all clock domains

Signed-off-by: Theodor Stana <t.stana@cern.ch>
added wb write function for slave interfaces to wishbone_pkg
Merge branch 'proposed_master' of ohwr.org:hdl-core-lib/general-cores into proposed_master
Moved sync chain out of gc_glitch_filt, added gc_glitch_filt doc

To make the design more modular, moved the synchronization chain out of
the gc_glitch_filt component. Made the necessary changes in the
components using the gc_glitch_filt.

Also added gc_glitch_filt documentation.

Signed-off-by: Theodor Stana <t.stana@cern.ch>
wb_uart: fix flow control on vuart rx path
Merge branch 'master' into proposed_master