New set of NPC SetPWM_Nx1 and SetPWM_Nx2 functions.

Added set of functions to the API for the NPC using the modified pin
mapping on the IoCU board for the NPC. Rack 1 NPC IoCU board was modified
in the Fall of 2013 and Rack 2 NPC IoCU board was brought up to rack 1
status today. Essentially the IoCU PCB changes made by Dr. Hasanzadeh to
the PWM pin traces was undone as this turned out not to be necessary for
the NPC PWM pin mapping. Here is a brief overview.

void SetPWM_Na1(...) {EPwm1Regs.CMPA.half.CMPA = (Uint16)(D);}
void SetPWM_Na3(...) {EPwm1Regs.CMPB = (Uint16)(D);          }
void SetPWM_Na2(...) {EPwm2Regs.CMPA.half.CMPA = (Uint16)(D);}
void SetPWM_Na4(...) {EPwm2Regs.CMPB = (Uint16)(D);          }

void SetPWM_Nb1(...) {EPwm3Regs.CMPA.half.CMPA = (Uint16)(D);}
void SetPWM_Nb3(...) {...
void SetPWM_Nc2(...) {EPwm4Regs.CMPA.half.CMPA = (Uint16)(D);}
void SetPWM_Nc4(...) {...

void SetPWM_Nc1(...) {EPwm5Regs.CMPA.half.CMPA = (Uint16)(D);}
void SetPWM_Nc3(...) {...
void SetPWM_Nc2(...) {EPwm6Regs.CMPA.half.CMPA = (Uint16)(D);}
void SetPWM_Nc4(...) {...

a, b, and c refer to the phase. 1 and 2 refer to the switch number. In a
3-level diode-clamped NPC phase leg there are 4 IGBTs - number them
1,2,3,4 starting at the top. Also, switches 1,3 are complements that need
deadtime and 2,4 are complements that need deadtime.

SetPWM_Na1( ) is used to set the duty on switch 1 and the PWM settings in
the API create a complement on switch 3 along with deadband time.

SetPWM_Na2( ) is used to set the duty on switch 2 and the PWM settings in
the API create a complement on switch 4 along with deadband time.

The SetPWM_Na3( ) and SetPWM_Na4( ) were simply added for completeness as
the prior set of PWM functions for the AFE/INV allowed for setting of the
complemented switch duty cycle as well. The current code design direction       of the PWM register settings are to have switches 3 and 4 be complements        as described in this commit so use of these two functions may not ever          be needed.

Description on the PWM PCB trace/pin remapping that make this possible is
described below.
(this functionality is not possible with the PCB traces used on the
AFE-INV).

History

This stems back to the fact that the 28335 PWM modules 1-6 have an A and B
channel where B has been setup to be the complement of A with a deadband
time to prevent shoot-through. For the back-to-back 2-level converters the
originally mapped IoCU PCB traces had to be modified due to some
communication errors during the design about where each PWM channel was         to be routed. Dr. Hasanzadeh fixed this probelm by adding jumpers to            the PCB traces.

Long story short the back-to-back 2-level converters use PWM 1,2,3 for AFE
with 1A and 1B being for phase A half-bridge, 2A and 2B for phase B, and
finally 3A and 3B for phase C.
PWM 4,5,6 are for INV with 4A and 4B for phase A, 5A and 5B for phase B, and 6A and 6B for phase C.

This turns out not to be suitable for the 3-level NPC topology. The
original NPC design uses two half-bridges and a diode half-bridge for each
phase leg. The IGBT half-bridges have one ribbon cable for the 2 PWM pulses
that connects the IoCU board to the CONCEPT gate driver board atop the
IGBT module.

If the IoCU board for the AFE/INV is used for the NPC then switches 1,2 will be
complements, and 3,4 will be complements. This is not satisfactory as
switches 1,3 need to be complements and 2,4 need to be complements. Fortunately the original PWM pin mapping in the original PCB design are
OK! Hooray! This means that a simple revision back to the original PCB
traces will solve the issue (this is not as simple as it sounds as undoing
the PCB trace rework by Dr. Hasanzadeh is minor surgery on the PCB). This
PCB fix was completed on rack 2 NPC IoCU board today without too much
headache.

To sum up, the diagram below shows which PWM signal goes to the 4 switches
on each phase leg with the top switch at the top. 1A refers to PWM module 1
channel A, 1B for PWM module 1 channel B, etc.

NPC
PhaseA PhaseB PhaseC
1A     3A     5A
2A     4A     6A
1B     3B     5B
2B     4B     6B
First commit in ONRdemo branch.

This branch is meant to quickly bring the racks to a state where
all 4 DSPs can be programmed from the same CCS project. This means
having NPC code (PWMs disabled right now) to send the DAC values to
dSPACE as well as individual PWM enables for AFE and INV separated
for racks 1 and 2. This can be seen by the additional #ifdef npc
and #ifdef b2b.
Changed INV to closed loop references.

This commit was part of some documentation steps to show
others how to go through cloning a repo, checking out a
branch, making edits, making a commit, then pushing
changes to Github.
Added separate CAN address for rack 2 PWM enables.

Added a second pair of CAN addresses for rack 2 AFE and INV PWM enables.

Testing today consisted of testing each rack from AFE-INV(openloop)-NPC(diodes)
up to 5kW with NHR 9200 load. This followed by AFE-INV(closedloop)-NPC(diodes)
individually to the load. After connecting the NPC outputs together, the load
was apply first slowly up to 5kW then a 0-5kW step change. Then 5-8kW followed
by a 0-8kW step change. Final increase up to 10kW then 0-10kW. A previous
modification had rack 1 NPC input inductors at 0.6mH and rack 2 at 2.07mH
which caused an imperfect power balance.

The rack 1 inductors were changed back to the original 2.07mH set and 0-10kW
test was redone showing better power balance. However, even with closed loop
inverter control the output of the two NPCs in diode-rectifier mode had
a significant voltage drop under load.
Changed NPC DAC outputs to have Iabc
Merging ONRdemo
Merged in NPC controller code.
Added more NPC PWM debugging.
Added NPC CAN message for PWM enable.

Added NPC CAN messages and separate #defines for rk1 and rk2.
Modifying 3-level modulation

Previous PLECS simulations to mimic the shifted carrier strategy
presented in  Josep Pou's 2012 Transactions on Power Electronics
paper were wrong. This revision doesn't scale the modulation
indices by 0.5 followed by +0.5 shift. Instead modulation in its
original [-1 1] form is given to SetPWM_Na1((dra)*PWM_PD); and
a +1.0 shift dra signal is given to SetPWM_Na2((dra+1.0)*PWM_PD);

PLECS simulations trying to match the PLECS "Symmetrical PWM (3-leve)"
block for the "Negative carrier: Shifted" proved to match the paper
rather than the "Negative carrier: flipped".

Hopefully this commit will lead to a working NPC 3-level rectifier
with zero-sequence injection described by Josep Pou!