FIFO related optimizations

I noticed that we were processing all the FIFO data 32 bytes at a time. For example, if we had 90KB waiting in the FIFO, we would copy 32 bytes, put it into our internal read buffer, try to decode opcodes (which would usually fail because we don't have enough data, for example for vertex uploads which we process all at once), then do the same for the next 32 bytes, etc.

This PR changes this behavior to copy and decode as much as we can, which **should** be a safe optimization that improves GPU thread performance.
This fifo registers are likely shared with the cpu thread, so we have to care about the order of this atomic reads.