softpipe: handle vertex texture sampling when using llvm for draw

Pretty trivial, just fill in the offsets and such. The implementation
is near 100% copy and paste from llvmpipe. Should be useful for debugging.

No piglit change when not using SOFTPIPE_USE_LLVM=1.
Now that it can do the same tests with and without using llvm for vs/gs,
with llvm more pass, the only things failing only with llvm seems to be
edgeflags tests and vs/gs-pow-float-float (and for the latter I'm not
convinced the zero tolerance it requires is somehow mandated by glsl).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
gallivm: fix somewhat broken NaN behavior for exp2

I actually screwed that up in 754319490f6946a9ad5ee619822d5fe4254e6759,
mistakenly thinking the code actually wanted the non-nan result before.
So, introduce that missing nan behavior case and use that instead.
For sse, there's no actual change in the resulting code at all, the fallback
code wouldn't have done the right thing though.
Of course, the actual issue I saw with pow() was completely unrelated...

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
mesa: Delete ctx->GeometryProgram.Cache.

The VertexProgram and FragmentProgram have a Cache member for dealing
with fixed function programs.  There are no fixed function geometry
programs, so this should never have existed, and was just copy and
pasted.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
glsl: Eliminate ir_variable::data.atomic.buffer_index

Just use ir_variable::data.binding... because that's the where the
binding is stored for everything else that can use layout(binding=).

Valgrind massif results for a trimmed apitrace of dota2:

                  n        time(i)         total(B)   useful-heap(B) extra-heap(B)    stacks(B)
Before (32-bit): 50 40,564,927,443       69,185,408       63,683,871     5,501,537            0
After  (32-bit): 74 40,580,119,657       69,186,544       63,506,327     5,680,217            0

Before (64-bit): 59 36,822,048,449       96,526,888       89,113,000     7,413,888            0
After  (64-bit): 89 36,822,971,897       96,526,616       88,735,296     7,791,320            0

A real savings of 173KiB on 32-bit and 368KiB on 64-bit.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
glsl: Use a single bit for the dual-source blend index

The only values allowed are 0 and 1, and the value is checked before
assigning.

Valgrind massif results for a trimmed apitrace of dota2:

                  n        time(i)         total(B)   useful-heap(B) extra-heap(B)    stacks(B)
Before (32-bit): 74 40,580,119,657       69,186,544       63,506,327     5,680,217            0
After  (32-bit): 76 40,572,916,873       68,831,248       63,328,783     5,502,465            0

Before (64-bit): 89 36,822,971,897       96,526,616       88,735,296     7,791,320            0
After  (64-bit): 60 36,822,640,058       96,526,824       88,735,296     7,791,528            0

A real savings of 173KiB on 32-bit and no change on 64-bit.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
glsl: Use bit-flags image attributes and uint16_t for the image format

All of the GL image enums fit in 16-bits.

Also move the fields from the anonymous "image" structucture to the next
higher structure.  This will enable packing the bits with the other
bitfield.

Valgrind massif results for a trimmed apitrace of dota2:

                  n        time(i)         total(B)   useful-heap(B) extra-heap(B)    stacks(B)
Before (32-bit): 76 40,572,916,873       68,831,248       63,328,783     5,502,465            0
After  (32-bit): 70 40,577,421,777       68,487,584       62,973,695     5,513,889            0

Before (64-bit): 60 36,822,640,058       96,526,824       88,735,296     7,791,528            0
After  (64-bit): 74 37,124,603,758       95,891,808       88,466,712     7,425,096            0

A real savings of 346KiB on 32-bit and 262KiB on 64-bit.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
freedreno/ir3: detect scheduler fail

There are some cases where the scheduler can get itself into impossible
situations, by scheduling the wrong write to pred or addr register
first.  (Ie. it could end up being unable to schedule any instruction if
some instruction which depends on the current addr/reg value also
depends on another addr/reg value.)

To solve this we'd need to be able to insert extra mov instructions
(which would also help when register assignment gets into impossible
situations).  To do that, we'd need to move the nop padding from sched
into legalize.

But to start with, just detect when we get into an impossible situation
and bail, rather than sitting forever in an infinite loop.  This way it
will at least fall back to the old compiler, which might even work if
you are lucky.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno/ir3: add TXB

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno/ir3: fix potential null ptr deref

Fix potential segfault in debug code.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
st/hgl: Move st_manager create/destroy into hgl state_tracker
st/hgl: Move st_visual create/destroy into hgl state_tracker
ilo: replace cmd by dw0 in GPE

With e3c251071b0c9396c3ec76d1cf943c60ae297281, the magic values are gone.  We
no longer need "cmd" to hide them.  Replace it by dw0.
ilo: fix bound check for 3DSTATE_URB_VS

Fix max/min entries on GEN7.5 GT2/GT3.
ilo: set INTEL_RELOC_GGTT only on GEN6

We asked MI commands to use GGTT only on GEN6.
i965: Use unreachable() to silence warning.

brw_meta_fast_clear.c:211:17: warning: 'x_scaledown' may be used
uninitialized in this function [-Wmaybe-uninitialized]
    unsigned int x_scaledown, y_scaledown;

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/vec4: Update register coalescing test.

In commit 04895f5c I added support for reswizzling writemasks. This test
was checking that we didn't support this.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82881
i965: Add 2x MSAA support to Broadwell fast clear code.

According to the cited documentation section (but in the newer docs),
x_scaledown is the same for 2x and 4x MSAA.

+47 piglits.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83081
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
i965/vec4: inline generate_vec4_instruction() within generate_code()

Suggested by Matt. This patch combines and moves back the code-generation
functions from generate_vec4_instruction() into generate_code(). Makes
generate_code() a bit larger, but helps us to count loops in a
straightforward manner.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
i965/vec4/fs: Count loops in shader debug

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
glsl: Add ir_unop_saturate

Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>