cappuccino: lsu: move dc_sdat assign inside FEATURE_DATACACHE!="NONE"

Otherwise dc_sdat will be assigned twice when data cache is disabled.
Fix bug, `spr_dmr2` is floating when `FEATURE_DEBUGUNIT!="NONE"`.
remove cache enable debug prints

verilator will turn the $time call in those into a systemc libcall,
even when generating pure c++.
This kind of debug prints are anyway more suited for monitors,
so remove it from here.
Merge remote-tracking branch 'official/master'
Caches: Support multiple ways

Adds support for more than two ways. The memories are accordingly
replicated, the status vector extended, and some extra multiplexing
added. The caches still use LRU and utilize the optimized LRU unit.
Caches: Rename index->tag

The index points to the offset in the cache and tag memory. The tag is
the part left of the index in the address and it is stored in the tag
memory at the addressed index, not the index is stored in the tag.

Some beautification and documentation
Caches: Optimized LRU unit

This is the generic LRU unit. It uses an optimized vector which is of
size (NUMWAYS*(NUMWAYS-1))>>1. The content of the vector is the
reduced set of direct comparisons (x<y) where x is older than y. As
the module forbids x is equally old as y we have a symmetric behaviour
(x<y)=!(y<x).

For four ways the vector is then:

history [5:0] = {(2<3),(1<3),(1<2),(0<3),(0<2),(0<1)}

Further details, the instantiation and the algorithm itself are
documented in the module.
Caches: Support multiple ways

Adds support for more than two ways. The memories are accordingly
replicated, the status vector extended, and some extra multiplexing
added. The caches still use LRU and utilize the optimized LRU unit.
dcache: save copy of tag data on refill

The data read from the tag memory might be change during a refill,
so it's necessary to keep a copy around until the data is written back.

9e5a414 Caches: Support multiple ways
removed the old tag saving code, and correctly replaced it in the icache,
but the respective change was omitted from the dcache changes.
dcache: invalidate from READ state

If an invalidate request would occur while in READ state,
the request would be indefinitely ignored.
This adds a state change to the IDLE state on the invalidate signal,
which will assert the correct address and continue to the INVALIDATE state.
Multicore: Add core identifier

The core identifier can be read from SPR group 0 (system) at address
128 (newly assigned). Furthermore it is possible to read the number of
processor cores in a cluster via register 129. Both can apparently not
be written.

The registers are set via ports, which allow easier use in verilated
models or similar.

fix sprs
fix
Merge branch 'master' into multicore
Merge remote-tracking branch 'openrisc/master' into multicore
WIP: add support for l.lwa/l.swa atomic instructions
cappucino-ctrl: Add two ISRs in multicore mode

We need something like shadow registers in multicore mode as we need
to do clean calculations on exceptions. Add two ISRs (ISR0 and ISR1)
which are used as scratch registers on exceptions.
Debug: Execution traceport

The execution traceport traces all executed program counters, the
respective instruction and accesses to the register file with this
instruction. A rudimentary set of trace actions can be implemented in
a synthesizable way.

Set FEATURE_TRACEPORT_EXEC="ENABLED" to enable this trace port.

Add monitor for simulation.
WIP: Add snoop port