Masked Vector Load and Store Intrinsics.
Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores.
Added SDNodes for masked operations and lowering patterns for X86 code generator.
Examples:
<16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask)
declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask)

Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch.

http://reviews.llvm.org/D6191



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222632 91177308-0d34-0410-b5e6-96231b3b80d8
Tablegen output formatting fixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222633 91177308-0d34-0410-b5e6-96231b3b80d8
Add missing override keywords.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222634 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] Fixes bug in build_vector v4x32 lowering

r222375 made some improvements to build_vector lowering of v4x32 and v4xf32 into an insertps, but it missed a case where:

1. A single extracted element is used twice.
2. The lower of the two non-zero indexes should be preserved, and the higher should be used for the dest mask.

This caused a crash, since the source value for the insertps ends-up uninitialized.

Differential Revision: http://reviews.llvm.org/D6377

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222635 91177308-0d34-0410-b5e6-96231b3b80d8
Converted back to Unix format (after my last commit 222632)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222636 91177308-0d34-0410-b5e6-96231b3b80d8
Detect best type for some static index tables instead of just using uint32_t to reduce total data size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222643 91177308-0d34-0410-b5e6-96231b3b80d8
Support: Add *cast_or_null<> for pointer wrappers

Fill in omission of `cast_or_null<>` and `dyn_cast_or_null<>` for types
that wrap pointers (e.g., smart pointers).

Type traits need to be slightly stricter than for `cast<>` and
`dyn_cast<>` to resolve ambiguities with simple types.

There didn't seem to be any unit tests for pointer wrappers, so I tested
`isa<>`, `cast<>`, and `dyn_cast<>` while I was in there.

This only supports pointer wrappers with a conversion to `bool` to check
for null.  If in the future it's useful to support wrappers without such
a conversion, it should be a straightforward incremental step to use the
`simplify_type` machinery for the null check.  In that case, the unit
tests should be updated to remove the `operator bool()` from the
`pointer_wrappers::PTy`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222644 91177308-0d34-0410-b5e6-96231b3b80d8
InstCombine: Don't assume DataLayout is always available

We tried to get the result of DataLayout::getLargestLegalIntTypeSize but
we didn't have a DataLayout.  This resulted in opt crashing.

This fixes PR21651.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222645 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] Improved target specific combine on VSELECT dag nodes.

This patch teaches function 'transformVSELECTtoBlendVECTOR_SHUFFLE' how to
convert VSELECT dag nodes to shuffles on targets that do not have SSE4.1.
On pre-SSE4.1 targets, we can still perform blend operations using movss/movsd.

Also, removed a target specific combine that performed a premature lowering of
VSELECT nodes to target specific MOVSS/MOVSD nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222647 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][microMIPS] Implement disassembler support for 16-bit instructions

With the help of new method readInstruction16() two bytes are read and
decodeInstruction() is called with DecoderTableMicroMips16, if this fails
four bytes are read and decodeInstruction() is called with
DecoderTableMicroMips32.

Differential Revision: http://reviews.llvm.org/D6149


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222648 91177308-0d34-0410-b5e6-96231b3b80d8
Removing a variable that is initialized but never read. The original author has been alerted to the warning, in case this variable is meant to be used. Fixes -Werror builds in the meantime.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222649 91177308-0d34-0410-b5e6-96231b3b80d8
Replace a comment that says 'unreachable' with llvm_unreachable in TableGen AsmWriter output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222650 91177308-0d34-0410-b5e6-96231b3b80d8
[Mips] Update MIPS relocations list

No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222651 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][microMIPS] Implement 16-bit instructions registers including ZERO instead of S0

Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17.

Differential Revision: http://reviews.llvm.org/D5780


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222652 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructions

Differential Revision: http://reviews.llvm.org/D5122


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222653 91177308-0d34-0410-b5e6-96231b3b80d8
Added comment about llvm_execute_on_thread waiting for thread to complete.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222654 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][microMIPS] Fix JRADDIUSP instruction

Fix JRADDIUSP instruction, remove delay slot flag because this instruction
doesn't have delay slot.

Differential Revision: http://reviews.llvm.org/D6365


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222658 91177308-0d34-0410-b5e6-96231b3b80d8
InstCombine: Don't create an unused instruction

We would create an instruction but not inserting it.
Not inserting the unused instruction would lead us to verification
failure.

This fixes PR21653.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222659 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Adding zxtb instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222660 91177308-0d34-0410-b5e6-96231b3b80d8
Adding const iterator to MCInst. http://reviews.llvm.org/D6359

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222661 91177308-0d34-0410-b5e6-96231b3b80d8