u_vbuf: Simplify the format fallback translation.

Individual caps made supporting new fallbacks more complicated than it
needed to be.  Instead, just make a table of fallbacks at context init
time.

v2: Fix inverted "do we need to install vbuf?" flagging caught by Marek.

Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
u_vbuf: Add a few more format fallbacks.

Fixes piglit draw-vertices and gl-2.0-vertexattribpointer on vc4, where
I'm only advertising R32F to RGBA32F support so far.

Note: regresses gl-1.5-normal3b3s-invariance due to introduced flushes and
missing depth buffer load/store support in the driver.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
vc4: Fix LT/GE set-0-or-1 compares.

We were using the integer sub, which worked for the common case of EQ and
NE.  Fixes fs-lessThan-ivec2-ivec2 and other tests.
vc4: Ignore WADDRs from the other half of the instruction when merging.

This allows setting the opposite-side WADDR to NOP (a non-zero value) in
qpu_* helpers, so that we don't need to qpu_inst() merge them with NOPs
all the time just to get the waddr set.
vc4: Merge qpu_a_NOP() and qpu_m_NOP to a single qpu_NOP() helper.

Now that qpu_inst() ignores the WADDR from the other half of the
instruction, we can set both the ADD and MUL WADDRs in the NOP helper.
Thanks to that, we also no longer need to qpu_inst(NOP, NOP).
vc4: Set the other WADDR in the qpu instruction helpers.

Now you don't need to qpu_inst() your instruction with a NOP to get the
other waddr set.
vc4: Stop doing qpu_inst(add, NOP) or qpu_inst(NOP, mul).

Now that the extra WADDR is set, we can knock this off.  Saves a lot of
typing, and makes this code much more legible.
r300g: handle PIPE_BIND_BLENDABLE

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
r600g: only set PIPE_BIND_BLENDABLE if colorbuffer rendering is supported

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
radeonsi: handle PIPE_BIND_BLENDABLE

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
glsl: Remove bogus "OUPTUT" token

This is never used. There is another token "OUTPUT" which the lexer can
generate, though. This has been around since the dawn of time; is most
likely a typo.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
docs: Update who is working on tessellation

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
ilo: replace domains by reloc flags

It is simpler and is supported by the kernel.  It cannot be used with
libdrm_intel yet though.
ilo: remove max_batch_size

It is used to derive an artificial limit on max relocs per bo.  We choose not
to export it anymore.
ilo: rename intel_bo_map_unsynchronized()

Rename it to intel_bo_map_gtt_async().
ilo: use genhw command opcodes

Replace ILO_GPE_MI and ILO_GPE_CMD with magic values by descriptive genhw
macros.
st/vdpau: fix vlVdpOutputSurfaceRender(Output|Bitmap)Surface

Correctly handle that the source_surface is only optional.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80561

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
vl/compositor: set the scissor before clearing the render target

Otherwise we clear areas that shouldn't be cleared.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
radeon/uvd: fix field handling on R6XX style UVD

The first UVD generation can only do frame based output.

Signed-off-by: Christian König <christian.koenig@amd.com>
radeon/uvd: remove comment about RV770

It doesn't seem to support field based decode after testing.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>