arm/crypto: Add optimized AES and SHA1 routines

Add assembler versions of AES and SHA1 for ARM platforms.  This has provided
up to a 50% improvement in IPsec/TCP throughout for tunnels using AES128/SHA1.

Platform   CPU SPeed    Endian   Before (bps)   After (bps)   Improvement

IXP425      533 MHz      big     11217042        15566294        ~38%
KS8695      166 MHz     little    3828549         5795373        ~51%

Signed-off-by: David McCullough <ucdevel@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

ARM: 7626/1: arm/crypto: Make asm SHA-1 and AES code Thumb-2 compatible

This patch fixes aes-armv4.S and sha1-armv4-large.S to work
natively in Thumb.  This allows ARM/Thumb interworking workarounds
to be removed.

I also take the opportunity to convert some explicit assembler
directives for exported functions to the standard
ENTRY()/ENDPROC().

For the code itself:

  * In sha1_block_data_order, use of TEQ with sp is deprecated in
    ARMv7 and not supported in Thumb.  For the branches back to
    .L_00_15 and .L_40_59, the TEQ is converted to a CMP, under the
    assumption that clobbering the C flag here will not cause
    incorrect behaviour.

    For the first branch back to .L_20_39_or_60_79 the C flag is
    important, so sp is moved temporarily into another register so
    that TEQ can be used for the comparison.

  * In the AES code, most forms of register-indexed addressing with
    shifts and rotates are not permitted for loads and stores in
    Thumb, so the address calculation is done using a separate
    instruction for the Thumb case.

The resulting code is unlikely to be optimally scheduled, but it
should not have a large impact given the overall size of the code.
I haven't run any benchmarks.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Tested-by: David McCullough <ucdevel@gmail.com> (ARM only)
Acked-by: David McCullough <ucdevel@gmail.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7723/1: crypto: sha1-armv4-large.S: fix SP handling

Make the SHA1 asm code ABI conformant by making sure all stack
accesses occur above the stack pointer.

Origin:
http://git.openssl.org/gitweb/?p=openssl.git;a=commit;h=1a9d60d2

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Cc: stable@vger.kernel.org
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7837/3: fix Thumb-2 bug in AES assembler code

commit 40190c85f427dcfdbab5dbef4ffd2510d649da1f upstream.

Patch 638591c enabled building the AES assembler code in Thumb2 mode.
However, this code used arithmetic involving PC rather than adr{l}
instructions to generate PC-relative references to the lookup tables,
and this needs to take into account the different PC offset when
running in Thumb mode.

Change-Id: I0d036eaa94dabefa0a025d522f415c663d00ae9f
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
qseecom: increase load app timer delay

double load app timer delay to 4000ms

Signed-off-by: Zhen Kong <zkong@codeaurora.org>
qseecom: Add support for PFE feature

Add key management support for crypto HW used for
PFE (per file encryption) features.

Change-Id: Ic0664973d9a4099f76d7b3040f0f81df8465cf71
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
qseecom: Check for FDE/PFE feature

Add checks for PFE/FDE feature before executing anything
related to the feature.

Change-Id: I575d4d4eea29fd9ae59e47805793f2416a97f5b9
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
qseecom: Change pr_warning message to pr_debug

Change warning message to debug message to reduce the excessive logging.
These changes are applicable only if any process is trying to interrupt
the blocking listener services.

Change-Id: Ie1c9af0daf16ef2c39e198f30b0151e2246d79e3
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
qseecom: Validate shared buffer length & virtual address

Return -EINVAL if virtual addr of shared buffer is NULL or
shared buffer length is 0

Change-Id: I44369bf12ddafa63b71ee54496eb86b2615d4322
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
qseecom: update clock ref count when bus scaling timer is running

When there are multiple enable/dislable clock operations, ce clock
ref count is not updated correctly when the timer to disable clock
is running. Specifically, the ref count is not decreased when the
old operation is finished and then we reset clock for the new enable
clock. Thus, the ce clock is not disabled after all operation are
completed due to incorrect clk ref count. We make a change to
decrease clock reference count before reset timer, when the timer
is running, then clock is disabled when all ce clock operations
finish and the timer expires.

Change-Id: If71fd526acd9a74bf21731841fae0b98e76a89b5
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
qseecom: Fix clock get failures

Pass the device node with of_node to clk_get(), to get the clock struct.
This patch fixes the issue by passing proper device handle with of_node
to clock APIs to get the appropriate clock node.

Change-Id: I01a2caf7d86a4399b1bb4a455ef8ecbbad5ad9a2
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
qseecom: Validate the pointer returned by ion_import_dma_buf

Do a "IS_ERR_OR_NULL" check for the return value of
ion_import_dma_buf.

Change-Id: Iaac8b59b1f076d002430e0e6aba055bd88c83ed7
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
qseecom: Validate pointer offset in qseecom_send_modfd_cmd

Validate cmd_req_buf pointer offset in qseecom_send_modfy_cmd, and
make sure cmd buffer address to be within shared bufffer.

Change-Id: I431511a92ab2cccbc2daebc0cf76cc3872689a97
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
qseecom: change qseecom bus scaling timer operation

To ensure ce clock is not disabled before tz operation is completed,
we delete the old timer when tz side operation begins, and then add
a new timer after tz operation is completed.

Change-Id: I4bc8fe3d9305cc1ed5db8e6490832fcc791ef3d7
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
qseecom: Ensure CE clk is managed properly

clk access ref count is not updated correctly when issuing a
request that requires enabling clk. this results in leaving the
clk on during regular operation resulting in failure of the
device to go into low power mode.

Change-Id: I80232433ff09277fe83d78142dcec75e7493d96e
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Revert QSEECOM changes until new TZ is available.

Revert "qseecom: Ensure CE clk is managed properly"

This reverts commit abcde2912b7625e756d62b06fe3c3f7579761a6d.

Revert "qseecom: change qseecom bus scaling timer operation"

This reverts commit b115fc248be58a085d5b3c5456a5042e85599f12.
Revert "Revert QSEECOM changes until new TZ is available."

This reverts commit 8e1653290d2cfbca3c4c956ff539188562494354.
qseecom: Fix issue related to retrieving pipe for PFE

Incorrect  parameter is overwritten when reading information
related to what pipe is used for PFE feature.

Change-Id: I6747fa0b8b99d937475d3d12e2f9ed9a723f91bb
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
qseecom: Verify shared buffer size

Valiade ION allocated shared buffer mapped in kernel space
is of same size as allocated in user space.

Change-Id: I4df11a9ce824756b7544377e0d944948838dfd54
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
qseecom: Check the return value of "ion_phys"

Check for return value of "ion_phys" and handle
the error cases appropriately.

Change-Id: Ib4f24af24de2b2553ed91479f46b2f79e0be0446
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
qseecom: Replace kzalloc with ion_alloc

Allocate memory to common lib through kzalloc issues no page errors due to
higher order memory request. So allocate the memory from the heap specially
dedicated to QSEECOM.

Change-Id: Ice4a609d6791ce5adc84b9882231def31674f461
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
qseecom: register bus bandwidth mode when loading app

When there are multiple running qseecom clients, ce clock may be disabled
by one client while TZ is still loading another client's app, which will
lead to load app failure. So, we make a change to register bus bandwidth
mode before loading app and avoid to disable clock when current bandwidth
mode is not INACTIVE.

Change-Id: I1727f6fc038baf95da39089e1f0faefe42f3d40c
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
qseecom: change bus scale up mode in resume function

The maximum bus bandwidth mode supported by bus bandwidth setting
function is 3 (i.e., HIGH), then to scale up bus bandwidth based on
cumulative mode may prevent us from updating the bus bandwidth
correctly when cumulative mode is greater than 3 (which is the case
if there are concurrent applications running). Thus, we made a
change to scale up bus bandwidth mode to at most 3 in qseecom
resume function.

Change-Id: I3ec6eedace2fa2ea7de519df307c3ff9b193c910
Signed-off-by: Zhen Kong <zkong@codeaurora.org>