Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)
Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh
Fixed memory corruption in passes/abc/blifparse.cc
Added support for `line compiler directive
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
(see https://github.com/cliffordwolf/yosys/pull/28)
Merged addition of SED makefile variable from github.com/Siesh1oo/yosys
(see https://github.com/cliffordwolf/yosys/pull/28)
OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/yosys
(see https://github.com/cliffordwolf/yosys/pull/28)
 - Makefile: resolve merge conflict.
 - Makefile: export PATH=${DESTDIR}/bin:$(PATH) and (DY)LD_LIBRARY_PATH, to make sure our local copies of built executables and libraries are used.
 - Makefile: use find expression in target 'yosys-svgviewer' to find svgviewer binary (qmake will build into .app package on OSX).
 - Makefile: make 'test' target dependent on $(TARGETS) and $(EXTRA_TARGETS) to make sure that minisat is built.
 - Makefile: fix typo in LDFLAGS: obviously -L, not -I is required here
 - Makefile: include $(PWD) in PATH, since 'make test' can happen before 'make install'.
Rebase to cliffordwolf repo HEAD finished.
 - Makefile: don't add '-g' after '-ggdb' to CXXFLAGS