More interrupt fixes

- Fix case where instructions were lost when an interrupt was dispatched
in the same cycle an instruction from a different thread was being
retired. An interrupt can only be raised if that thread is retiring
an instruction or if there is no instruction.
- Need to piggyback interrupts on events in the simulation reorder queue
because an interrupt can occur the same cycle a store is commited to the
store queue.  These would clobber one another otherwise.
- Add ability to handle interrupts in randomized test generator (currently
disabled)
- Change the way the last PC is recorded in simulator.  Since not every
instruction generates a cosimulation event, we can reliably infer it
in the simulator. It is now passed as a parameter in the event. This means
we can't really validate that the hardware is doing the right thing with
this register, since we take its word.

There still is an infinite interrupt loop in the randomized test
stream where the return from interrupt jumps to the instruction before
the return.