clk: sunxi: Support factor clocks with N factor starting not from 0

The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a
N multiplier factor that starts from 1, not 0.

This patch adds an option to the factor clk driver's config data
structures to specify the base value of N.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk: sunxi: Add post clk divider for factor clocks

Some factor clocks, mostly PLLs, have an extra fixed divider just before
the clock output. Add an option to the factor clk driver config data to
specify this divider.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk: sunxi: Fix rate_recalc for sun6i PLL1

PLL1 on sun6i is a factor clock with the N multiplier factor starting
from 1. Set the .n_start field in the clock data to match.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk: sunxi: Fix PLL6 calculation on sun6i

The N factor for PLL6 counts from 1 to 32, as specified in the A23
manual, and shown in Allwinner's original A31 code.

Also the PLL6 factors alone calculate the clock rate for PLL6x2, not
the normal halved output for PLL6. This is what the factors clk
.recalc_rate callback expects.

This patch fixes the N factor in the clock driver, and adds a post
PLL divider of 2 to calculate the rate for PLL6.

A further patch (to the DT) should add a fixed-factor x2 clock as
the PLL6x2 output.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: sun6i: DT: Add PLL6x2 fixed-factor clock

Some modules use the PLL6x2 output from PLL6. Add a fixed-factor clock
for this.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk: sunxi: Add sun6i MBUS clock support

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk: sunxi: Add support for table-based divider clocks

A few of the clock modules have odd dividers, such as
the 2 lowest dividers being the same (2), or have the
same divider when the highest bit is set.

This patch adds support for optional divider tables,
so the clock framework will know about the odd values.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clk: sunxi: Add A23 clocks support

The clock control unit on the A23 is similar to the one found on the A31.

The AHB1, APB1, APB2 gates on the A23 are almost identical to the ones
on the A31, but some outputs are missing.

The main CPU PLL (PLL1) however is like that on older Allwinner SoCs, such
as the A10 or A20, but the N factor starts from 1 instead of 0.

This patch adds support for PLL1 and all the basic clock gates.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk: sunxi: Add A23 APB0 support to sun6i-a31-apb0-clk

The A23 has an almost identical PRCM clock tree. The difference in
the APB0 clock is the smallest divisor is 1, instead of 2.

This patch extends the sun6i-a31-apb0-clk driver to take divider
tables associated to compatibles, and adds a compatible for the A23
variant.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk: sunxi: Add A23 specific compatible to sun6i-a31-apb0-gates-clk

The sun6i-a31-apb0-gates-clk driver is generic in that it supports
the "clock-indicies" DT property with "clock-output-names" to list
the valid clock gate bits.

However this might lead one to assume that the clock in the A23 is
the same as the A31. To make it clear, we add a new compatible for
the A23, "allwinner,sun8i-a23-apb0-gates-clk".

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
pinctrl: sunxi: Add A23 PIO controller support

The A23 uses the same pin controller as previous SoC's from Allwinner.
Add support for the pins controlled by the main PIO controller.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
pinctrl: sunxi: Add A23 R_PIO controller support

The A23 has a R_PIO pin controller, similar to the one found on the A31 SoC.
Add support for the pins controlled by the R_PIO controller.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
mfd: sun6i-prcm: Add support for Allwinner A23 PRCM

The Allwinner A23 SoC has a PRCM unit like the previous A31 SoC.
The differences are the AR100 clock can no longer be modified,
the APB0 clock has different divisors, and some clock gates are
gone.

This patch adds a compatible with a modified subdevice list for
the A23.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: sunxi: Introduce Allwinner A23 support

The Allwinner A23 is a dual-core Cortex-A7-based SoC. It re-uses most of
the IPs found in previous SoCs, notably the A31.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: sunxi: Add earlyprintk support using R_UART (sun6i/sun8i)

sun6i/sun8i have a UART in the RTC block group, which can be used
as an early console. This is most useful on sun8i as UART0 is muxed
with MMC0, which is not available if we boot from MMC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sunxi: Add Allwinner A23 dtsi

The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores
and a Mali-400MP2 GPU.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: sun8i: dt: Add Ippo-q8h v5 support

The Ippo-q8h is a tablet circiut board commonly found in cheap Android
tablets with A23 SoCs. There are at least 2 versions of the board, with
different peripherals, such as WiFi chips.

This patch add supports for v5 of such boards, which has a ESP8089 WiFi
chip (not supported) connected to mmc1.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>