tcg-sparc: Support addsub2_i64

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Use ADDXC in addsub2_i64

On T4 and newer Sparc chips we have an add-with-carry insn
that takes its input from %xcc instead of %icc.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Fix setcond_i32 uninitialized value

We failed to swap c1 and c2 correctly for NE c2 == 0.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Use ADDXC in setcond_i64

Similar to the ADDC tricks we use in setcond_i32.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Rename ADDX/SUBX insns

The pre-v9 ADDX/SUBX insns were renamed ADDC/SUBC for v9.
Standardizing on the v9 name makes things less confusing.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Use UMULXHI instruction

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg: Compress TCGLabelQemuLdst

Use 1 32-bit word instead of 6.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-aarch64: Use 32-bit loads for qemu_ld_i32

The "old" qemu_ld opcode did not specify the size of the result,
and so we had to assume full register width.  With the new opcodes,
we can narrow the result.

Signed-off-by: Richard Henderson <rth@twiddle.net>