msm: spm: T6: modify power collapse seq for kraitv3

High sleep current observed due to L2 cache not going into
power collapse in special cases.

While analyzing, a timing issue was found that can manifest itself when the
clamp signal is asserted during the Krait CPU1 power collapse sequence.
When it occurs, the issue causes an L2 FIFO to falsely believe that it
has data to return to CPU1 when it does not.The condition isnt detected until
later when CPU0 and the L2 attempt to collapse.

This condition keeps the L2 from going idle which keeps it from power
collapsing after both CPUs have collapsed.  This in turn prevents the
RPM from enabling a system low power state (VDD minimization).
The issue is likely process/temp/voltage dependent.

HW team recommended a workaround, the details are as below.

Add commands to the Krait CPU power collapse SPM sequences to assert
Krait CPU reset prior to asserting the CPU clamp signal and de-assert
CPU reset after the CPU clamp is asserted.
Since the CPU clocks are gated (by the first SPM command in the
sequence), and the clamp is applied, the Krait CPU will do nothing
when its reset is de-asserted.

The workaround involves changing both CPU power collapse SPM sequences
(Power Collapse with and without RPM notification).

CRs-fixed: 518750
Change-Id: I62c76f49a96a8cb6ecf67733ae9a7ff1a79a76f7
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>