hdl/top/top/afc_v1/*: add divclk generic to PLL

This allow us to select a broader range of frequencies,
in order to generate a 100 MHz clock from a 125 MHz clock
source, for instance
hdl/top/afc_v1/*: fix wrong timing constraint in UCF file

This constraint was causing conflicts with the other
ones and a wrong PLL PERIOD contraint was taken into
account
hdl/top/afc_v1/*: change MMCM_ADV to PLLE2_ADV primitive

In the 7-SERIES families, the PLL and MMCM are two separate
primitives, very similar to each other. In other to reduce
the number of MMCM usage, we changed it to PLL here