[Hexagon] Converting from ADD_rr to A2_add which has encoding bits.
Adding test to show correct instruction selection and encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222249 91177308-0d34-0410-b5e6-96231b3b80d8
[Reassociate] Use test cases that can actually be optimized to verify optional
flags are cleared.  The reassociation pass was just reordering the leaf nodes
in the previous test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222250 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Make sure resource descriptors are always stored in SGPRs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222253 91177308-0d34-0410-b5e6-96231b3b80d8
Fix an incorrect chain operand when expanding INSERT_VECTOR operations through the stack.

Patch by Daniil Troshkov!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222254 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64] Don't optimize all compare instructions.

"optimizeCompareInstr" converts compares (cmp/cmn) into plain sub/add
instructions when the flags are not used anymore. This conversion is valid for
most instructions, but not all. Some instructions that don't set the flags
(e.g. sub with immediate) can set the SP, whereas the flag setting version uses
the same encoding for the "zero" register.

Update the code to also check for the return register before performing the
optimization to make sure that a cmp doesn't suddenly turn into a sub that sets
the stack pointer.

I don't have a test case for this, because it isn't easy to trigger.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222255 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Move SIFixSGPRCopies to inst selector passes

This should expose more of the actually used VALU
instructions to the machine optimization passes.

This also should help getting i1 handling into a better state.
For not entirly understood reasons, this fixes the split-scalar-i64-add.ll
test where a 64-bit add would only partially be moved to the VALU
resulting in use of undefined VCC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222256 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel][AArch64] Follow-up fix for "Fix shift-immediate emission for "zero" shifts."

Shifts also perform sign-/zero-extends to larger types, which requires us to emit
an integer extend instead of a simple COPY.

Related to PR21594.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222257 91177308-0d34-0410-b5e6-96231b3b80d8
Add support for LLVM_USE_SANITIZER=Thread

Summary: This will help in testing libc++ and libc++abi with tsan.

Reviewers: samsonov

Reviewed By: samsonov

Subscribers: samsonov, llvm-commits

Differential Revision: http://reviews.llvm.org/D6283

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222258 91177308-0d34-0410-b5e6-96231b3b80d8