rtc: Add an RTC API, and implement it for x86.

This CL adds an API for RTC drivers, and implements its two functions,
rtc_get and rtc_set, for x86's RTC. The function which resets the clock when the
CMOS as lost state now uses the RTC driver instead of accessing the those
registers directly.

BUG=None
TEST=Built and booted on Link with the event log code modified to use
the RTC interface. Verified that the event times were accurate.
BRANCH=nyan

Original-Change-Id: Ifa807898e583254e57167fd44932ea86627a02ee
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197795
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>

This is the first half of the patch.
(cherry picked from commit 9e0fd75142d29afe34f6c6b9ce0099f478ca5a93)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I159f9b4872a0bb932961b4168b180c087dfb1883
Reviewed-on: http://review.coreboot.org/7889
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
drivers/spi: add support for another Spansion chip

Add the device ID definitions and properties for the SPI chip used on
the AP148 board (Google Storm).

BUG=chrome-os-partner:27784
TEST=manual
   . with the rest of the patches applied AP148 boots all the way to
     trying to read the payload.

Original-Change-Id: I5a0e5c9d3cc9ea81bc5227c0fbc1d0a5fc7bec27
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197895
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit a7c69981b18ac6b1158273596b94df0def65963d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I14e2f4f8f691a7db6ed596a3440914e08680867b
Reviewed-on: http://review.coreboot.org/7931
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Provide a common CBFS wrapper for SPI storage

Coreboot has all necessary infrastructure to use the proper SPI flash
interface in bootblock for CBFS. This patch creates a common CBFS
wrapper which can be enabled on different platforms as required.

COMMON_CBFS_SPI_WRAPPER, a new configuration option, enables the
common CBFS interface and prevents default inclusion of all SPI chip
drivers, only explicitly configured ones will be included when the new
feature is enabled. Since the wrapper uses the same driver at all
stages, enabling the new feature will also make it necessary to
include the SPI chip drivers in bootblock and romstage images.

init_default_cbfs_media() can now be common for different platforms,
and as such is defined in the library.

BUG=none
TEST=manual
   . with this change and the rest of the patches coreboot on AP148
     comes up all the way to attempting to boot the payload (reading
     earlier stages from the SPI flash along the way).

Original-Change-Id: Ia887bb7f386a0e23a110e38001d86f9d43fadf2c
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197800
Original-Tested-by: Vadim Bendebury <vbendeb@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 60eb16ebe624f9420c6191afa6ba239b8e83a6e6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I7b0bf3dda915c227659ab62743e405312dedaf41
Reviewed-on: http://review.coreboot.org/7932
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
drivers/spi: Prepare Spansion driver for use in CBFS wrapper

Since the same driver is going to be used at all coreboot stages, it
can not use malloc() anymore. Replace it with static allocation of the
driver container structure.

The read interface is changed to spi_flash_cmd_read_slow(), because of
the problems with spi_flash_cmd_read_fast() implementation. In fact
there is no performance difference in the way the two interface
functions are implemented.

BUG=chrome-os-partner:27784
TEST=manual
  . with all patches applied coreboot proceeds to attempting to load
    the payload.

Original-Change-Id: I1c7beedce7747bc89ab865fd844b568ad50d2dae
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197931
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 57ee2fd875c689706c70338e073acefb806787e7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9d9e7e343148519580ed4986800dc6c6b9a5f5d2
Reviewed-on: http://review.coreboot.org/7933
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
SPI: Fix Eon support

The Eon SPI25 code had a number of issues:
 - fix page write calculation
 - fix erase segment
 - fix id check
 - fix sector size
 - make commands EN25 generic
This makes the code similar to other SPI25 devices used in coreboot.

BUG=chrome-os-partner:25907
BRANCH=baytrail(rambi)
TEST=Read and write MRC and ELOG on Glimmer with Eon device.

Original-Change-Id: I7667eab28b850790d92a591c869788d51c26a56c
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/198323
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Marc Jones <marc.jones@se-eng.com>
Original-Tested-by: Marc Jones <marc.jones@se-eng.com>
(cherry picked from commit 2ee0da695bf6a6c6aedc0dd2b3a3b7c9c3165bca)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8917e778cd62f3745189336d23c0c6118887d893
Reviewed-on: http://review.coreboot.org/7934
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
SPI: Add Eon EN25S64 support.

BUG=chrome-os-partner:25907
BRANCH=baytrail(rambi)
TEST=Read and write MRC and ELOG on Glimmer with Eon device.

Original-Change-Id: If883ff6eb14dd49a06f57a01ca61661854ded78d
Original-Reviewed-on: https://chromium-review.googlesource.com/198324
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Marc Jones <marc.jones@se-eng.com>
Original-Tested-by: Marc Jones <marc.jones@se-eng.com>
(cherry picked from commit 536c34c2d92178f4e62b8ca7cfffceaf80a305f6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I199451ed2b29c55bfb5e1487afa8cf3b9978e63e
Reviewed-on: http://review.coreboot.org/7935
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
baytrail: Add defines and functions for GPNCORE

BUG=chrome-os-partner:25159
BRANCH=firmware-rambi-5216.B
TEST=Build pass for Rambi

Original-Change-Id: I049f9254fe25aabf13d891579444bba2cfcf68c5
Original-Change-Id: Ib7c814660262e2507813ee5970190f98530dfe5e
Original-Signed-off-by: Kein Yuan <kein.yuan@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197984
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit dd05055f2f74fc0e4875733c0e5dedcbae302bfa)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Iee01407a73bec420ab47d07524a3f1fd0f4d9817
Reviewed-on: http://review.coreboot.org/7892
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
libpayload: Provide selfboot function.

The calling convention of payload entry function is different by architecture.
For example, X86 takes no arguments and ARM needs first param to be a
cb_header_ptr*.

To help payloads load and execute other payloads easily and correctly, we should
provide the selfboot() function in libpayload, using same prototype as defined
in coreboot environment.

BUG=none
TEST=emerge-nyan libpayload # pass
BRANCH=none

Original-Change-Id: I8f1cb2c0df788794b2f6f7f5500a3910328a4f84
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199503
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 1e916cf021ce68886eb9668982c392eadedc7b7e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I7279ef27f49ef581d25a455dd8f1f2f7f1ba58cb
Reviewed-on: http://review.coreboot.org/7907
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
libpayload: Fix libpayload build compilation warnings

When emerging libpayload a warning is generated about selfboot() being
defined without a prior prototype.

Add cbfs.h when CBFS use if compiled fixes the warning.

BUG=none
TEST=build rambi storm nyan_big
  verify that there is no compilation warnings thrown any more

Original-Change-Id: Ic9cb5571f708bb006a0d477e451fd1f3b3eb833f
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200099
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 7e4aa17936b70dd08f58b3a55c6db55ea03709d7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie3baaaca82fb6ec432860c638acb2a3ef9451469
Reviewed-on: http://review.coreboot.org/7909
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
ipq/arm: Redesign hooks for bootblock

The following patches had to be squashed
to properly build all the different ARM boards.

ipq8064: storm: re-arrange bootblock initialization

The recent addition of the storm bootblock initialization broke
compilation of Exynos platforms. The SOC specific code needs to be
kept in the respective source files, not in the common CPU code.

As of now coreboot does not provide a separate SOC initialization API.
In general it makes sense to invoke SOC initialization from the board
initialization code, as the board knows what SOC it is running on.

Presently all what's need initialization on 8064 is the timer. This
patch adds the SOC initialization framework for 8064 and moves there
the related code.

BUG=chrome-os-partner:27784
TEST=manual
  . nyan_big, peach_pit, and storm targets build fine now.

Original-Change-Id: Iae9a021f8cbf7d009770b02d798147a3e08420e8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197835
(cherry picked from commit 3ea7307b531b1a78c692e4f71a0d81b32108ebf0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

arm: Redesign mainboard and SoC hooks for bootblock

This patch makes some slight changes to the way bootblock_cpu_init() and
bootblock_mainboard_init() are used on ARM. Experience has shown that
nearly every board needs either one or both of these hooks, so having
explicit Kconfigs for them has become unwieldy. Instead, this patch
implements them as a weak symbol that can be overridden by mainboard/SoC
code, as the more recent arm64_soc_init() is also doing.

Since the whole concept of a single "CPU" on ARM systems has kinda died
out, rename bootblock_cpu_init() to bootblock_soc_init(). (This had
already been done on Storm/ipq806x, which is now adjusted to directly
use the generic hook.) Also add a proper license header to
bootblock_common.h that was somehow missing.

Leaving non-ARM32 architectures out for now, since they are still using
the really old and weird x86 model of directly including a file. These
architectures should also eventually be aligned with the cleaner ARM32
model as they mature.

BRANCH=None
BUG=chrome-os-partner:32123
TEST=Booted on Pinky. Compiled for Storm and confirmed in the
disassembly that bootblock_soc_init() is still compiled in and called
right before the (now no-op) bootblock_mainboard_init().

Original-Change-Id: I57013b99c3af455cc3d7e78f344888d27ffb8d79
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/231940
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 257aaee9e3aeeffe50ed54de7342dd2bc9baae76)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id055fe60a8caf63a9787138811dc69ac04dfba57
Reviewed-on: http://review.coreboot.org/7879
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
ipq8064: make timer services available

Make sure it is initialized at different stages.

BUG=chrome-os-partner:27784
TEST=manual
. not much at this point, just verified that it compiles

Original-Change-Id: I343e7a6648e2ca935606cd76befd204aabd93726
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on:
https://chromium-review.googlesource.com/196592
(cherry picked from commit aedc41924313e5c21aef97b036f5a0643d59082d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I4a90ae5ba6c9a561b7d5c938d18b6ea2b855855f
Reviewed-on: http://review.coreboot.org/7981
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
ipq8064: SOC UART driver belongs in the SOC directory

Move the driver to where it belongs.

BUG=chrome-os-partner:27784
TEST=none

Original-Change-Id: Iee33de0b29a6bb86ba7c37e7e89aabc0fee42e80
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196658
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 64afb0a2ac9b6cd4c202b879a484220e70ff5bbe)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Iee33de0b29a6bb86ba7c37e7e89aabc0fee42e80
Reviewed-on: http://review.coreboot.org/7871
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
ipq8064: prepare include files before adding UART driver

These patch modifies .h files to match the coreboot API. A few more
significant changes are:

 - UART specific fields removed from common board structure in cdp.h.
   These fields are set at compile time in u-boot (where this
   structure comes from), they will be set in a different structure in
   the UART driver in an upcoming patch.

 - an inline wrapper is added in gpio.h to provide GPIO API the UART
   driver expects.

 - the ipq_configure_gpio() is passed the descriptor placed in ro data.

BUG=chrome-os-partner:27784
TEST=none

Original-Change-Id: Id49507fb0c72ef993a89b538cd417b6c86ae3786
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196661
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit ea400f1b720eb671fa411c5fd1df7efd14fdacd6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I2c7be09675b225de99be3c94b22e9ee2ebb2cb9a
Reviewed-on: http://review.coreboot.org/7873
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
ipq8064: prepare uart driver for use in coreboot

The IO accessor wrappers are used to allow integer register addresses.
A structure defining UART interface configuration is declared and
defined. A few long lines are wrapped. Interface functions are renamed
to match the wrapper API.

cdp.c is edited to fit into coreboot compilation environment, and the
only function required by the UART driver if exposed, the rest are
compiled out for now.

BUG=chrome-os-partner:27784
TEST=after all patches are applied the serial console on AP148 becomes
      operational.

Original-Change-Id: I80c824d085036c0f90c52aad77843e87976dbe49
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196662
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 5e9af53a069cd048334a3a28f0a4ce9df7c96992)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I80c824d085036c0f90c52aad77843e87976dbe49
Reviewed-on: http://review.coreboot.org/7874
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>