Add Imagination Technologies to the vendors in llvm::Triple

Summary: This is a pre-requisite for supporting the mips-img-linux-gnu triple in clang.

Differential Revision: http://reviews.llvm.org/D4435


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212626 91177308-0d34-0410-b5e6-96231b3b80d8
Fix for PR20059 (instcombine reorders shufflevector after instruction that may trap)

In PR20059 ( http://llvm.org/pr20059 ), instcombine eliminates shuffles that are necessary before performing an operation that can trap (srem).

This patch calls isSafeToSpeculativelyExecute() and bails out of the optimization in SimplifyVectorOp() if needed.

Differential Revision: http://reviews.llvm.org/D4424



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212629 91177308-0d34-0410-b5e6-96231b3b80d8
removed duplicate testcase


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212632 91177308-0d34-0410-b5e6-96231b3b80d8
Make AArch64FastISel::EmitIntExt explicitly check its source and destination types

This is a follow up to r212492. There should be no functional difference, but
this patch makes it clear that SrcVT must be an i1/i8/16/i32 and DestVT must be
an i8/i16/i32/i64.

rdar://17516686

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212633 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] AVX512: Enable it in the Loop Vectorizer

This lets us experiment with 512-bit vectorization without passing
force-vector-width manually.

The code generated for a simple integer memset loop is properly vectorized.
Disassembly is still broken for it though :(.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212634 91177308-0d34-0410-b5e6-96231b3b80d8
Update ReleaseNotes to mention Atomic NAND semantic changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212635 91177308-0d34-0410-b5e6-96231b3b80d8
TargetRegisterInfo: Remove function that fell out of use years ago.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212636 91177308-0d34-0410-b5e6-96231b3b80d8
Change an assert() to a diagnostic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212637 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: Better codegen for storing to __fp16.

Storing will generally be immediately preceded by rounding from an f32
or f64, so make sure to match those patterns directly to convert into the
FPR16 register class directly rather than going through the integer GPRs.

This also eliminates an extra step in the convert-from-f64 path
which was first converting to f32 and then to f16 from there.

rdar://17594379

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212638 91177308-0d34-0410-b5e6-96231b3b80d8
Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine.

Do this if the truncate is free and the select is legal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212640 91177308-0d34-0410-b5e6-96231b3b80d8
Use simpler constructor for range adapter.

It is a good idea, it's slightly clearer and simpler. Unfortunately
the headline news is: we save one line!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212641 91177308-0d34-0410-b5e6-96231b3b80d8
Decouple llvm::SpecialCaseList text representation and its LLVM IR semantics.

Turn llvm::SpecialCaseList into a simple class that parses text files in
a specified format and knows nothing about LLVM IR. Move this class into
LLVMSupport library. Implement two users of this class:
  * DFSanABIList in DFSan instrumentation pass.
  * SanitizerBlacklist in Clang CodeGen library.
The latter will be modified to use actual source-level information from frontend
(source file names) instead of unstable LLVM IR things (LLVM Module identifier).

Remove dependency edge from ClangCodeGen/ClangDriver to LLVMTransformUtils.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212643 91177308-0d34-0410-b5e6-96231b3b80d8
Recommit r212203: Don't try to construct debug LexicalScopes hierarchy for functions that do not have top level debug information.

Reverted by Eric Christopher (Thanks!) in r212203 after Bob Wilson
reported LTO issues. Duncan Exon Smith and Aditya Nandakumar helped
provide a reduced reproduction, though the failure wasn't too hard to
guess, and even easier with the example to confirm.

The assertion that the subprogram metadata associated with an
llvm::Function matches the scope data referenced by the DbgLocs on the
instructions in that function is not valid under LTO. In LTO, a C++
inline function might exist in multiple CUs and the subprogram metadata
nodes will refer to the same llvm::Function. In this case, depending on
the order of the CUs, the first intance of the subprogram metadata may
not be the one referenced by the instructions in that function and the
assertion will fail.

A test case (test/DebugInfo/cross-cu-linkonce-distinct.ll) is added, the
assertion removed and a comment added to explain this situation.

Original commit message:

If a function isn't actually in a CU's subprogram list in the debug info
metadata, ignore all the DebugLocs and don't try to build scopes, track
variables, etc.

While this is possibly a minor optimization, it's also a correctness fix
for an incoming patch that will add assertions to LexicalScopes and the
debug info verifier to ensure that all scope chains lead to debug info
for the current function.

Fix up a few test cases that had broken/incomplete debug info that could
violate this constraint.

Add a test case where this occurs by design (inlining a
debug-info-having function in an attribute nodebug function - we want
this to work because /if/ the nodebug function is then inlined into a
debug-info-having function, it should be fine (and will work fine - we
just stitch the scopes up as usual), but should the inlining not happen
we need to not assert fail either).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212649 91177308-0d34-0410-b5e6-96231b3b80d8
[SDAG] Make the new zext-vector-inreg node default to expand so targets
don't need to set it manually.

This is based on feedback from Tom who pointed out that if every target
needs to handle this we need to reach out to those maintainers. In fact,
it doesn't make sense to duplicate everything when anything other than
expand seems unlikely at this stage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212661 91177308-0d34-0410-b5e6-96231b3b80d8
[dfsan] Handle bitcast aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212668 91177308-0d34-0410-b5e6-96231b3b80d8
[x86] Refactor some of the new code for lowering v16i8 shuffles to
remove duplication and make it easier to select different strategies.

No functionality changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212674 91177308-0d34-0410-b5e6-96231b3b80d8
Fix types in documentation.

The examples were using f32, but the IR type is called float

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212675 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Add support for llvm.convert.{to|from}.fp16

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212676 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64]Fix an assertion failure in DAG Combiner about concating 2 build_vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212677 91177308-0d34-0410-b5e6-96231b3b80d8
SpecialCaseList: use std::unique_ptr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212678 91177308-0d34-0410-b5e6-96231b3b80d8