Randomize more than 32 bits of disconnected inputs
Fix ROMs for Verilog synthesis

We were previously emitting syntactically incorrect Verilog.

I refactored the way ROMs are handled.  We no longer associate the ROM
type with data emission.  Since ROM inherits from Vec, there's just too
much baggage.  Instead, the data is now contained in a ROMData class,
and ROMRead treats ROMData as one of its inputs.  Thus, multiple ROM
ports share the same data store (unlike in previous Verilog output).
For multi-ported ROMs, this is potentially beneficial for C++/Flo/FPGA.