[FIX] Fix timing issues in PCIe PCP

- Increase mn_pcp slow bridge address width
- Move CRA and shared onchip memory to slow bridge
- Enable pipelining for PCIe BAR0 connection to SRAM

Change-Id: Iae213ae717e992aeb22bb097b7892aac37cb1606
[FIX] Relax SRAM write timing

Increase to two write cycles in the SRAM controller.

Change-Id: Ifee5d119a3df684bb4b3f5b41b7e540bd104d442
[FIX] Remove RBF generation in Antares Quartus project

Change-Id: I7109f6865aab170ab49a2b7026b9d5fb9eefdf87
[FEATURE] Add heap size limit to drivers and apps Nios tools

This enables to set a heap size limit in the board.settings file.

Change-Id: I0468fbe95b9380ff834b4d5d8ff7a828cfedbb78
[TASK] Set heap size limit for Antares to 256 kB

Change-Id: Iaf2047e86b38ec19607ac6a4858bf8466e86fe40