CHROMIUM: iommu/tegra124: smmu: optionaly AHB enables SMMU

SMMU used to depend on AHB bus. AHB driver needs to be populated and
AHB_XBAR_CTRL_SMMU_INIT_DONE bit needs to be set earliear than SMMU
being populated. Later Tegra SoC (>= T124) doesn't need AHB to enable
SMMU on AHB_XBAR_CTRL for AHB_XBAR_CTRL_SMMU_INIT_DONE any more. This
setting bit is now optional, depending on DT passing ahb phandle or
not.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>

Patch posted upstream at:
      http://patchwork.ozlabs.org/patch/297110/

BUG=none
TEST=applied this and the rest of the patches in the series, make sure
kernel works.

Change-Id: I721e0f168010db7803f1f541ae40fd5142c1f810
Reviewed-on: https://chromium-review.googlesource.com/180887
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: iommu/tegra124: smmu: convert swgroup ID to asid offset

Provide a conversion table from swgroup ID to MC_SMMU_<swgroup
name>_ASID_0 register offset to support non-linear conversion. This
conversion used to be exactly linear but after T124 we need a
conversion table to support non-linear cases. We would also need
another table to convert swgroup ID to HOTRESET bit.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>

Patch posted upstream at:
      http://patchwork.ozlabs.org/patch/297111/

BUG=none
TEST=applied this and the rest of the patches in the series, make sure
kernel works.

Change-Id: I793b5ba8cce76b54e3b84f39b8bf1696481a6f0e
Reviewed-on: https://chromium-review.googlesource.com/180888
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: iommu/tegra124: smmu: add support platform data

The later Tegra SoC(>= T124) has more registers for
MC_SMMU_TRANSLATION_ENABLE_*. Now those info is provided as platfrom
data. If those varies a lot on SoCs in the future, we can consider
putting them into DT later.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>

Patch posted upstream at:
      http://patchwork.ozlabs.org/patch/297112/

BUG=none
TEST=applied this and the rest of the patches in the series, make sure
kernel works.

Change-Id: Icb9362e98a7b08890d363341aae57cc4f7a9a4ce
Reviewed-on: https://chromium-review.googlesource.com/180889
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: iommu/tegra124: smmu: support more than 32 bit pa

Add support for more than 32 bit physical address. If physical
address space is 32bit, there will be no register write
happening. Based on Pavan's internal patch.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Cc: Pavan Kunapuli <pkunapuli@nvidia.com>

Patch posted upstream at:
      http://patchwork.ozlabs.org/patch/297113/

BUG=none
TEST=applied this and the rest of the patches in the series, make sure
kernel works.

Change-Id: I2990437ddd4e0ffe0c810266aae4c202b8763fae
Reviewed-on: https://chromium-review.googlesource.com/180890
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
CHROMIUM: iommu/tegra124: smmu: {TLB,PTC} reset value per SoC

T124 has some new register bits in {TLB,PTC}_CONFIG:

- TLB_RR_ARB and PTC_REQ_LIMIT
- TLB_ACTIVE_LINES 0x20 instead of 0x10

They are defined as platform data now.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>

Patch posted upstream at:
      http://patchwork.ozlabs.org/patch/297114/

BUG=none
TEST=applied this and the rest of the patches in the series, make sure
kernel works.

Change-Id: I5b94b499458e60abf27320cd121f335a42426300
Reviewed-on: https://chromium-review.googlesource.com/180891
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
CHROMIUM: iommu/tegra124: smmu: adjust TLB_FLUSH_ASID bit range

TLB_FLUSH_ASID bit range depends on the number of asids to support
other number than the current 4, especially for a new Tegra124. Based
on Terje's internal patch.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Cc: Terje Bergstrom <tbergstrom@nvidia.com>

Patch posted upstream at:
      http://patchwork.ozlabs.org/patch/297115/

BUG=none
TEST=applied this and the rest of the patches in the series, make sure
kernel works.

Change-Id: I0a42e9bcc92a0fcb6ea70b828d012a0db706a072
Reviewed-on: https://chromium-review.googlesource.com/180892
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
CHROMIUM: iommu/tegra124: smmu: add multiple asid_security support

In Tegra124 the number of MC_SMMU_ASID_SECURITY_# registers
increased. Now this info is provided as platfrom data. If no platfrom
data the default valude(1) is used.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>

Patch posted upstream at:
      http://patchwork.ozlabs.org/patch/298944/

BUG=none
TEST=applied this and the rest of the patches in the series, make sure
kernel works.

Change-Id: Icf565e69c0d8d814e2cc2ed946a6a6d701ec2aad
Reviewed-on: https://chromium-review.googlesource.com/180893
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
CHROMIUM: ARM: dts: tegra124: Add SMMU node

Add a DT entry for SMMU.

BUG=none
TEST=built kernel with the SMMU series and made sure kernel works.

Change-Id: I4a65d8382756ec0c52797abbadbf9aa99ab052fb
Signed-off-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180861
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
CHROMIUM: ARM: dts: nyan: Change "nvidia,memory-clients"

"nvidia,memory-clients" has been changed to "iommus" in the SMMU driver.

BUG=none
TEST=applied this and the rest of the patches in the series, make sure
kernel works.

Change-Id: Ia6249a6a3fde18e66852c73ee0cfc3d883230690
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/180894
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
CHROMIUM: ARM: dts: venice: fix build warning

Add address-cells and size-cells properities to memory-controller node.
This can fix the build warning

BUG=None
TEST=Built kernel and boot

Change-Id: Iec6c1ba1cce0279656a9a0a681d6020b49523ed3
Signed-off-by: Danny Huang <dahuang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/181087
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: smmu: Add swgid/asid mapping function

Host1x driver needs to get asid according to swgid.
So adding a function in smmu driver to do that.

BUG=none
TEST=built kernel with the SMMU series and made sure kernel works.

Change-Id: I4a45d9717ac3a3536216ee91000f1172f0765a65
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/180862
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
UPSTREAM: ARM: tegra: Add header file for pinctrl constants

This new header file defines pincontrol constants for Tegra to
use from Tegra's DTS file for pincontrol properties option.

BUG=none
TEST=tested with following commit that uses the defines.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Dylan Reid <dgreid@chromium.org>
(cherry picked from commit b758df2e2af6bbd100fad85473dcf49c2f31d39a)
(cherry picked from tree:
 git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git)

Change-Id: I17f6ef53c2048578b6188bf27f69c5f741b3dcdd
Reviewed-on: https://chromium-review.googlesource.com/181136
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
CHROMIUM: ARM: dts: tegra124: Use pinctrl defines.

Replace literal numbers with the defines provided by the recently added
pinctrl-tegra.h.  This makes the file easier to read and brings it
closer to the upstream tegra124 dts files.

BUG=none
TEST=Run C preprocessor across file before and after change, check there
is no difference.

Change-Id: I5984c779d2df5d8619398482ec328a436a98b87c
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181137
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: devfreq: Round frequencies in transition stats

Transition statistics required that the new frequency was *exactly*
as it was in the table. However, we may unexpectedly select a
frequency that is not in the table (i.e. thermal limit forces us to
select a bit lower frequency, the original DVFS table does not hold
for the current PLL for some reason, etc.)

This patch modifies transition table to select the best candidate
from the frequency table.

BUG=none
TEST=emerged kernel for nyan(Tegra124 Norrin) and made sure kernel boots.

Change-Id: Iab573eb785f08f28e4717b7937fdcc9e7118bb08
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180247
Reviewed-by: Dylan Reid <dgreid@chromium.org>
CHROMIUM: pwm-backlight: export pwm_backlight_parse_dt

We need a pwm_bl's function to set "check_fb" fops.
Currently because backlight driver utilizes DT,
so there is no way to do that unless we make this change.

BUG=none
TEST=emerged kernel for nyan (Tegra124 Norrin) and made sure kernel boots.

Change-Id: I856c6d33214d82f259336f28a8945e724d26c860
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/180276
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: ARM: dts: tegra124: Add Host1x devices

Add Tegra124 host1x devices like host1x/vic/gk20a in DT.

BUG=none
TEST=emerged kernel for nyan(Tegra124 Norrin) and made sure kernel boots.

Change-Id: If23599bac946d55fe9473699a655277649d79593
Signed-off-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180897
Commit-Queue: Andrew Chew <achew@nvidia.com>
Tested-by: Andrew Chew <achew@nvidia.com>
CHROMIUM: ARM: dts: tegra124: nyan: add node for the gpu rail

BUG=none
TEST=emerged kernel for nyan(Tegra124 Norrin) and made sure kernel boots.

Change-Id: Ib9abecad807875699865c325c968feee75f46dbf
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/180290
Tested-by: Mark Zhang <markz@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Revert "CHROMIUM: pinctrl: tegra124: add pinctrl driver for NVIDIA's Tegra124 SoC"

This reverts commit c0e15c1581a8609f9f95205ba0a7b6231dcce3ec.

This is being reverted so that the new upstread version can be pulled in.

BUG=None
TEST=Verified driver was removed.
CQ-DEPEND=CL:180925

Change-Id: Ie453bfa6298729500ceabbaa59177c0d21f56df7
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/180924
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
UPSTREAM: pinctrl: tegra: Add devicetree binding document for Tegra124

This device tree binding document describes the Tegra124 pincontrol
DT bindings. This document lists all valid properties, names, mux
options of Tegra124 pins.

Changes from V1:
- Referred the dt-binding header file on describing the nodes.

Changes from V2:
- Rewording reg properties.
- drop drv_type as it is not applicable.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

(cherry picked from commit 49a9ac222c73794df9282a75a6b4ef06d3b93f9d)

BUG=None
TEST=Verified kernel compiled and booted.

Change-Id: If0a8fd1e73efd4b54b74081104473f7ae8fb83e7
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/181280
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
UPSTREAM: pinctrl: tegra: add pinmux controller driver for Tegra124

This adds a driver for the Tegra124 pinmux, and required
parameterization data for Tegra124.

The driver uses the common Tegra pincontrol driver utility
functions to implement the majority of the driver.

This driver is not compatible with the earlier NVIDIA's SoCs,
hence add new compatibile as "nvidia,tegra124-pinmux".

Originally written by Ashwini Gguhe.
Thierry:
 - Cleanups in patches.
ldewangan:
 - Fix some entries for groups.
 - Fix MUX enums and group sequence.

Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
CC: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

BUG=None
TEST=Verified kernel compiled and booted.

(cherry picked from commit 1a16bee6bce39ca31724cf928dce19bd48d78df5)

Change-Id: I8fde0601dc61b8bcfa98edd80311bf37f942f54a
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/180925
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>