gcc/
	* ira.h (ira_finish_once): Delete.
	* ira-int.h (target_ira_int::~target_ira_int): Declare.
	(target_ira_int::free_ira_costs): Likewise.
	(target_ira_int::free_register_move_costs): Likewise.
	(ira_finish_costs_once): Delete.
	* ira.c (free_register_move_costs): Replace with...
	(target_ira_int::free_register_move_costs): ...this new function.
	(target_ira_int::~target_ira_int): Define.
	(ira_init): Call free_register_move_costs as a member function rather
	than a global function.
	(ira_finish_once): Delete.
	* ira-costs.c (free_ira_costs): Replace with...
	(target_ira_int::free_ira_costs): ...this new function.
	(ira_init_costs): Call free_ira_costs as a member function rather
	than a global function.
	(ira_finish_costs_once): Delete.
	* target-globals.c (target_globals::~target_globals): Call the
	target_ira_int destructor.
	* toplev.c: Include lra.h.
	(finalize): Call lra_finish_once rather than ira_finish_once.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215200 138bc75d-0d04-0410-961f-82ee72b054a4
AVX-512. Extend gather insn patterns.

gcc/
	* config/i386/sse.md
	(define_expand "<avx512>_gathersi<mode>"): Rename from
	"avx512f_gathersi<mode>".
	(define_insn "*avx512f_gathersi<mode>"): Use VI48F.
	(define_insn "*avx512f_gathersi<mode>_2"): Ditto.
	(define_expand "<avx512>_gatherdi<mode>"): Rename from
	"avx512f_gatherdi<mode>".
	(define_insn "*avx512f_gatherdi<mode>"): Use VI48F.
	(define_insn "*avx512f_gatherdi<mode>_2"): Use VI48F, add 128/256-bit
	wide versions.
	(define_expand "<avx512>_scattersi<mode>"): Rename from
	"avx512f_scattersi<mode>".
	(define_insn "*avx512f_scattersi<mode>"): Use VI48F.
	(define_expand "<avx512>_scatterdi<mode>"): Rename from
	"avx512f_scatterdi<mode>".
	(define_insn "*avx512f_scatterdi<mode>"): Use VI48F.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215201 138bc75d-0d04-0410-961f-82ee72b054a4
AVX-512.  Extend max/min insn patterns.

gcc/
	* config/i386/sse.md (VI128_256): Delete.
	(define_mode_iterator VI124_256): New.
	(define_mode_iterator VI124_256_AVX512F_AVX512BW): Ditto.
	(define_expand "<code><mode>3<mask_name><round_name>"): Delete.
	(define_expand "<code><VI124_256_AVX512F_AVX512BW:mode>3"): New.
	(define_insn "*avx2_<code><VI124_256:mode>3"): Rename from
	"*avx2_<code><mode>3<mask_name><round_name>" and update mode iterator.
	(define_expand "<code><VI48_AVX512VL:mode>3_mask"): New.
	(define_insn "*avx512bw_<code><VI48_AVX512VL:mode>3<mask_name>"): Ditto.
	(define_insn "<mask_codefor><code><mode>3<mask_name>"): Update mode
	iterator.
	(define_expand "<code><VI8_AVX2:mode>3"): Update pettern generation
	in presence of AVX-512.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215202 138bc75d-0d04-0410-961f-82ee72b054a4
AVX-512. Extend vpternlog, valign, vrotate insns.

gcc/
	* config/i386/sse.md
	(define_mode_iterator VI48_AVX512VL): New.
	(define_expand "<avx512>_vternlog<mode>_maskz"): Rename from
	"avx512f_vternlog<mode>_maskz" and update mode iterator.
	(define_insn "<avx512>_vternlog<mode><sd_maskz_name>"): Rename
	from "avx512f_vternlog<mode><sd_maskz_name>" and update mode iterator.
	(define_insn "<avx512>_vternlog<mode>_mask"): Rename from
	"avx512f_vternlog<mode>_mask" and update mode iterator.
	(define_insn "<mask_codefor><avx512>_align<mode><mask_name>"): Rename
	from "<mask_codefor>avx512f_align<mode><mask_name>" and update mode
	iterator.
	(define_insn "<avx512>_<rotate>v<mode><mask_name>"): Rename from
	"avx512f_<rotate>v<mode><mask_name>" and update mode iterator.
	(define_insn "<avx512>_<rotate><mode><mask_name>"): Rename from
	"avx512f_<rotate><mode><mask_name>" and update mode iterator.
	(define_insn "clz<mode>2<mask_name>"): Use VI48_AVX512VL mode iterator.
	(define_insn "<mask_codefor>conflict<mode><mask_name>"): Ditto.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215203 138bc75d-0d04-0410-961f-82ee72b054a4
[Ree] Ensure inserted copy don't change the number of hard registers

2014-09-12  Wilco Dijkstra  <wilco.dijkstra@arm.com>

  gcc/
    * ree.c (combine_reaching_defs): Ensure inserted copy don't change the
    number of hard registers.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215205 138bc75d-0d04-0410-961f-82ee72b054a4
[AArch64] Add cost handling of CALLER_SAVE_REGS and POINTER_REGS

2014-09-12  Wilco Dijkstra  <wdijkstr@arm.com>

  * gcc/config/aarch64/aarch64.c (aarch64_register_move_cost): Add cost handling
  of CALLER_SAVE_REGS and POINTER_REGS.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215206 138bc75d-0d04-0410-961f-82ee72b054a4
[AArch64] Fix cost for Q register moves

2014-09-12  Wilco Dijkstra  <wdijkstr@arm.com>

  * gcc/config/aarch64/aarch64.c (aarch64_register_move_cost): Fix Q register
  move handling.
  (generic_regmove_cost): Undo raised FP2FP move cost as Q register moves are
  now handled correctly.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215207 138bc75d-0d04-0410-961f-82ee72b054a4
[AArch64] Add regmove_costs for Cortex-A57 and A53

2014-09-12  Wilco Dijkstra  <wdijkstr@arm.com>

  * gcc/config/aarch64/aarch64.c: (cortexa57_regmove_cost): New cost table for
  A57.
  (cortexa53_regmove_cost): New cost table for A53.  Increase GP2FP/FP2GP cost
  to spilling from integer to FP registers.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215208 138bc75d-0d04-0410-961f-82ee72b054a4
2014-09-12  Marc Glisse  <marc.glisse@inria.fr>

gcc/
	* tree.c (integer_each_onep): New function.
	* tree.h (integer_each_onep): Declare it.
	* fold-const.c (fold_binary_loc): Use it for ~A + 1 to -A and
	-A - 1 to ~A.  Disable (X & 1) ^ 1, (X ^ 1) & 1 and ~X & 1 to
	(X & 1) == 0 for vector and complex.
gcc/testsuite/
	* gcc.dg/vec-andxor1.c: New file.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215209 138bc75d-0d04-0410-961f-82ee72b054a4
2014-09-12  Richard Biener  <rguenther@suse.de>

	PR middle-end/63237
	* gimple-fold.c (get_maxval_strlen): Gimplify string length.

	* g++.dg/torture/pr63237.C: New testcase.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215212 138bc75d-0d04-0410-961f-82ee72b054a4
Remove LIBGCC2_HAS_?F_MODE target macros.

This patch removes the LIBGCC2_HAS_{SF,DF,XF,TF}_MODE target macros,
replacing them by predefines with -fbuilding-libgcc, together with a
target hook that can influence those predefines when needed.

The new default is that a floating-point mode is supported in libgcc
if (a) it passes the scalar_mode_supported_p hook (otherwise it's not
plausible for it to be supported in libgcc) and (b) it's one of those
four modes (since those are the modes for which libgcc hardcodes the
possibility of support).  The target hook can override the default
choice (in either direction) for modes that pass
scalar_mode_supported_p (although overriding in the direction of
returning true when the default would return false only makes sense if
all relevant functions are specially defined in libgcc for that
particular target).

The previous default settings depended on various settings such as
LIBGCC2_LONG_DOUBLE_TYPE_SIZE, as well as targets defining the above
target macros if the default wasn't correct.

The default scalar_mode_supported_p only declares a floating-point
mode to be supported if it matches one of float / double / long
double.  This means that in most cases where a mode is only supported
conditionally in libgcc (TFmode only supported if it's the mode of
long double, most commonly), the default gets things right.  Overrides
were needed in the following cases:

* SFmode would always have been supported in libgcc (the condition was
  BITS_PER_UNIT == 8, true for all current targets), but pdp11
  defaults to 64-bit float, and in that case SFmode would fail
  scalar_mode_supported_p.  I don't know if libgcc actually built for
  pdp11 (and the port may well no longer be being used), but this
  patch adds a scalar_mode_supported_p hook to it to ensure SFmode is
  treated as supported.

* Certain i386 and ia64 targets need the new hook to match the
  existing cases for when XFmode or TFmode support is present in
  libgcc.  For i386, the hook can always declare XFmode to be
  supported - the cases where it's not are the cases where long double
  is TFmode, in which case XFmode fails scalar_mode_supported_p[*] -
  but TFmode support needs to be conditional.  (And of the targets not
  defining LIBGCC2_HAS_TF_MODE before this patch, some defined
  LONG_DOUBLE_TYPE_SIZE to 64, so ensuring LIBGCC2_HAS_TF_MODE would
  always be false, while others did not define it, so allowing it to
  be true in the -mlong-double-128 case.  This patch matches that
  logic, although I suspect all the latter targets would have been
  broken if you tried to enable -mlong-double-128 by default, for lack
  of the soft-fp TFmode support in libgcc, which is separately
  configured.)

  [*] I don't know if it's deliberate not to support __float80 at all
  with -mlong-double-128.

In order to implement the default version of the new hook,
insn-modes.h was made to contain macros such as HAVE_TFmode for each
machine mode, so the default hook can contain conditionals on whether
XFmode and TFmode exist (to match the hardcoding of a list of modes in
libgcc).  This is also used in fortran/trans-types.c; previously it
had a conditional on defined(LIBGCC2_HAS_TF_MODE) (a bit dubious,
since it ignored the value of the macro), which is replaced by testing
defined(HAVE_TFmode), in conjunction with requiring
targetm.libgcc_floating_mode_supported_p.

(Fortran is testing something stronger than that hook: not only is
libgcc support required, but also libm or equivalent.  Thus, it has a
test for ENABLE_LIBQUADMATH_SUPPORT in the case that the mode is
TFmode and that's not the same as any of the three standard types.
The old and new tests are intended to accept exactly the same set of
modes for all targets.)

Apart from the four target macros eliminated by this patch, it gets us
closer to eliminating LIBGCC2_LONG_DOUBLE_TYPE_SIZE as well, though a
few more places using that macro need changing first.

Bootstrapped with no regressions on x86_64-unknown-linux-gnu; also
built cc1 for crosses to ia64-elf and pdp11-none as a minimal test of
changes for those targets.

gcc:
	* target.def (libgcc_floating_mode_supported_p): New hook.
	* targhooks.c (default_libgcc_floating_mode_supported_p): New
	function.
	* targhooks.h (default_libgcc_floating_mode_supported_p): Declare.
	* doc/tm.texi.in (LIBGCC2_HAS_DF_MODE, LIBGCC2_HAS_XF_MODE)
	(LIBGCC2_HAS_TF_MODE): Remove.
	(TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): New @hook.
	* doc/tm.texi: Regenerate.
	* genmodes.c (emit_insn_modes_h): Define HAVE_%smode for each
	machine mode.
	* system.h (LIBGCC2_HAS_SF_MODE, LIBGCC2_HAS_DF_MODE)
	(LIBGCC2_HAS_XF_MODE, LIBGCC2_HAS_TF_MODE): Poison.
	* config/i386/cygming.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/darwin.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/djgpp.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/dragonfly.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/freebsd.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/gnu-user-common.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/i386-interix.h (IX86_NO_LIBGCC_TFMODE): Define.
	* config/i386/i386.c (ix86_libgcc_floating_mode_supported_p): New
	function.
	(TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Define.
	* config/i386/i386elf.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/lynx.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/netbsd-elf.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/netbsd64.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/nto.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/openbsd.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/openbsdelf.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/rtemself.h (IX86_NO_LIBGCC_TFMODE): Define.
	* config/i386/sol2.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/vx-common.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/ia64/elf.h (IA64_NO_LIBGCC_TFMODE): Define.
	* config/ia64/freebsd.h (IA64_NO_LIBGCC_TFMODE): Define.
	* config/ia64/hpux.h (LIBGCC2_HAS_XF_MODE, LIBGCC2_HAS_TF_MODE):
	Remove.
	* config/ia64/ia64.c (TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P):
	New macro.
	(ia64_libgcc_floating_mode_supported_p): New function.
	* config/ia64/linux.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/ia64/vms.h (IA64_NO_LIBGCC_XFMODE)
	(IA64_NO_LIBGCC_TFMODE): Define.
	* config/msp430/msp430.h (LIBGCC2_HAS_DF_MODE): Remove.
	* config/pdp11/pdp11.c (TARGET_SCALAR_MODE_SUPPORTED_P): New
	macro.
	(pdp11_scalar_mode_supported_p): New function.
	* config/rl78/rl78.h (LIBGCC2_HAS_DF_MODE): Remove.
	* config/rx/rx.h (LIBGCC2_HAS_DF_MODE): Remove.

gcc/c-family:
	* c-cppbuiltin.c (c_cpp_builtins): Define __LIBGCC_HAS_%s_MODE__
	macros for floating-point modes.

gcc/fortran:
	* trans-types.c (gfc_init_kinds): Check
	targetm.libgcc_floating_mode_supported_p for floating-point
	modes.  Check HAVE_TFmode instead of LIBGCC2_HAS_TF_MODE.

libgcc:
	* libgcc2.h (LIBGCC2_HAS_SF_MODE): Define using
	__LIBGCC_HAS_SF_MODE__.
	(LIBGCC2_HAS_DF_MODE): Define using __LIBGCC_HAS_DF_MODE__.
	(LIBGCC2_HAS_XF_MODE): Define using __LIBGCC_HAS_XF_MODE__.
	(LIBGCC2_HAS_TF_MODE): Define using __LIBGCC_HAS_TF_MODE__.
	* config/libbid/bid_gcc_intrinsics.h
	(LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Do not define.
	(LIBGCC2_HAS_XF_MODE): Define using __LIBGCC_HAS_XF_MODE__.
	(LIBGCC2_HAS_TF_MODE): Define using __LIBGCC_HAS_TF_MODE__.
	* fixed-bit.h (LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Do not define.
	(LIBGCC2_HAS_SF_MODE): Define using __LIBGCC_HAS_SF_MODE__.
	(LIBGCC2_HAS_DF_MODE): Define using __LIBGCC_HAS_DF_MODE__.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215215 138bc75d-0d04-0410-961f-82ee72b054a4
fix assert in hash_table pch routines

gcc/ChangeLog:

2014-09-12  Trevor Saunders  <tsaunders@mozilla.com>

	* hash-table.h (gt_pch_nx): don't call gt_pch_note_object within an
	assert.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215216 138bc75d-0d04-0410-961f-82ee72b054a4
fix ChangeLog typo

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215218 138bc75d-0d04-0410-961f-82ee72b054a4
	PR libstdc++/59603
	* include/bits/stl_algo.h (random_shuffle): Prevent self-swapping.
	* testsuite/25_algorithms/random_shuffle/59603.cc: New.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215219 138bc75d-0d04-0410-961f-82ee72b054a4
params 2 and 3 of reg_set_between_p

gcc/ChangeLog:
	* config/alpha/alpha.c (alpha_ra_ever_killed): Replace NULL_RTX
	with NULL when dealing with an insn.
	* config/sh/sh.c (sh_reorg): Strengthen local "last_float_move"
	from rtx to rtx_insn *.
	* rtl.h (reg_set_between_p): Strengthen params 2 and 3 from
	const_rtx to const rtx_insn *.
	* rtlanal.c (reg_set_between_p): Likewise, removing a checked cast.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215222 138bc75d-0d04-0410-961f-82ee72b054a4
	* include/debug/deque (__gnu_debug::deque): Make base class C++11
	allocator aware.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215223 138bc75d-0d04-0410-961f-82ee72b054a4
	PR c++/63201
	* decl.c (start_decl): Handle specialization of member variable
	template.
	* pt.c (check_explicit_specialization): Adjust error.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215226 138bc75d-0d04-0410-961f-82ee72b054a4
* config/msp430/msp430.md (extendhipsi2): Use 20-bit form of RLAM/RRAM.
(extend_and_shift1_hipsi2): Likewise.
(extend_and_shift2_hipsi2): Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215229 138bc75d-0d04-0410-961f-82ee72b054a4
Daily bump.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215233 138bc75d-0d04-0410-961f-82ee72b054a4
[Patch, microblaze]: Add optimized lshrsi3

When barrel shifter is not present, the immediate value
is greater than #5 and optimization is -OS, the
compiler will generate shift operation using loop.

Changelog

2013-11-26  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn

ChangeLog/testsuite

2014-02-12  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test.

Signed-off-by:Nagaraju <nmekala@xilix.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>