Prefetch sda symbol fix
Add HS to bfd
Typo
Refactoring
Infrastructure needed to add HS instructions (and adding XBFU)
Add STD/LDD ops
Select the proper register names for HS
Hard error when mixing ARCv2EM with ARCv2HS
Add HS instructions:  DMACH, DMACHU, DMPY, DMPYHU, MAC, MACU,VADDSUB2H, VSUB2H, and VSUBADD2H
Add all HS integral operations
Add VADD2H
 Add HS support
Fix AEX pattern for aux regs
Add HS floating point instructions
Add ACCL,ACCH registers for ARCv2
Selective truncate last bits of a pc relative relocation
Truncate all pc-relative relocation but  R_ARC_PC32  R_ARC_32_ME
Add HS
Arc: Fix changing of PC while in delay slot

In ARC PC register is a normal register so in most cases setting PC value is a
straightforward process: debugger just writes PC value. However it gets
trickier in case when current instruction is an instruction in delay slot. In
this case CPU will execute instruction at current PC value, then will set PC to
the current value of BTA register; also current instruction cannot be
branch/jump and some of the other instruction types. Thus if debugger would try
to just change PC value in this case, this instruction will get executed, but
then core will "jump" to the original branch target.

ARC provides following means to resolve this problem: - BTA register contains
address where core should jump after executing instruction in delay slot - Bit
DE in STATUS32 register indicates if current instruction is a delay slot
instruction. This bit is writable by debug host, which allows debug host to
prevent core from jumping after the delay slot instruction. At also works in
another directions: setting this bit will make core to treat any current
instructions as a delay slot instruction and to set PC to the current value of
BTA register.

To workaround issues with changing PC register while in delay slot instruction,
debugger should check for the STATUS32.DE bit and reset it if it is set. No
other change is required in this function. Most common case where this function
might be required is calling inferior functions from debugger.  Generic GDB
logic handles this pretty well: current values of registers are stored, value
of PC is changed (that is the job of this function), after inferior function is
executed, GDB restores all registers, which also means that core is returned to
its original state of being halted on delay slot instructions.

This method is useless for ARC 600, because it doesn't have externally exposed
BTA register. In the case of ARC 600 it is impossible to restore core to it's
state in all occasions thus core should never be halted (from the perspective
of debugger host) in the delay slot.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
Arc: Add helper functions to check for target architecture

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>