ARM: LoUIS cache maintenance API

 ARM v7 architecture introduced the concept of cache levels and related
 coherency requirements. New processors like A7 and A15 embed an
 L2 unified cache controller that becomes part of the cache level
 hierarchy. Some operations in the kernel like cpu_suspend and __cpu_disable
 does not require a flush of the entire cache hierarchy to DRAM but just the
 cache levels belonging to the Level of Unification Inner Shareable (LoUIS),
 which in most of ARM v7 systems correspond to L1.
 The current cache flushing API used in cpu_suspend and __cpu_disable,
 flush_cache_all(), ends up flushing the whole cache hierarchy since for
 v7 it cleans and invalidates all cache levels up to Level of Coherency
 (LoC) which cripples system performance when used in hot paths like hotplug
 and cpuidle.

 Therefore a new kernel cache maintenance API must be added to the
 cpu_cache_fns structure of pointers to cope with latest ARM system requirements.
 This patch adds flush_cache_louis() to the ARM kernel cache maintenance API.

 This function cleans and invalidates all data cache levels up to the
 level of unification inner shareable (LoUIS) and invalidates the instruction
 cache.

 The cpu_cache_fns struct reflects this change by adding a new function pointer
 that is initialized by arch specific assembly files.

 By default, all existing ARM archs do not instantiate any cache LoUIS function
 pointer, and flush_dcache_louis just falls back to flush_kern_all.

 Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>

Initial adaptation for msm8974

Signed-off-by: Jean Francis Dominique S. Mabalot <jfdsmabalot@redhat.com>