getset.h, cpuops.cpp, etc.: Check for the presence of interrupts after the end of each instruction on the 65C816 CPU, only once.

This code does not modify the timing of any SNES instruction, but modifies the timing of interrupts and events in the following ways:

* If the 65C816 would have asserted IRQ and NMI, or an interrupt and an event, among the cycles of the same instruction and the order in which they were asserted among its cycles matters, the ordering is now lost, and interrupt prioritisation code may be necessary.

The ordering of interrupts events disjoint by at least [Memory access * 2] + 2 65C816 cycles are not affected. The relationship between starting, continuing and finishing DMA and HDMA is not changed.