Fix debug build.
Wrong tree - reverting.
Pull up following revision(s) (requested by msaitoh in ticket #309):
	share/man/man7/Makefile: revision 1.31
	distrib/sets/lists/man/mi: revision 1.1491
Add missing src(7) reported by Patrick Welche.
Pull up following revision(s) (requested by msaitoh in ticket #310):
	sys/arch/x86/include/specialreg.h: revision 1.79-1.80
	usr.sbin/cpuctl/arch/i386.c: revision 1.59
	sys/arch/x86/include/cacheinfo.h: revision 1.19

Update some cpuid related values:
- Add XSAVECC, XGETBV, XSAVES, SMAP and PQE
- Change XINUSE to XGETBV
- Add new cache descripter value (0xc3)
- Update signatures for the follwing CPUs:
  - Core M-5xxx
  - Core i7 Extreme
  - Future Core (0x4e)
  - Future Xeon (0x56)
Pull up following revision(s) (requested by msaitoh in ticket #311):
	sys/dev/pci/ppb.c: revision 1.53
	sys/dev/pci/ppb.c: revision 1.54
	sys/dev/pci/pcireg.h: revision 1.96
- Modify message of PCIe capability version. This field (PCIE_XCAP_VER_MASK)
  is not specification's version number but the capability structure's version
  number. To avoid confusion, print "PCI Express capability version x".
- The max number of PCIe lane is not 16 but 32. Fix the bug using with macro.
- Use macro instead of magic number.
- Gb/s -> GT/s
Rename PCIE_XCAP_VER_* macros to avoid confusion.
Pull up following revision(s) (requested by msaitoh in ticket #312):
	sys/dev/pci/pci_subr.c: revision 1.130
	sys/dev/pci/pci_subr.c: revision 1.131
	sys/dev/pci/pci_subr.c: revision 1.132
	sys/dev/pci/pcireg.h: revision 1.97
	sys/dev/pci/pcireg.h: revision 1.98
	sys/dev/pci/pcireg.h: revision 1.99
	sys/dev/pci/pci_subr.c: revision 1.127
	sys/dev/pci/pci_subr.c: revision 1.128
	sys/dev/pci/pci_subr.c: revision 1.129
 Always print the Slot implemented bit in the PCIe Capabilities
Register using with onoff().
- Add some PCI subclass and interfaces.
- The interface of PCI_SUBCLASS_BRIDGE_RACEWAY is not decoded yet.
- Fix typo in a message.
- Add comment.
- Modify comment.
s/genric/generic/
Add comment.
Fix typo in comment.
 Fix a bug that the specification revision of the Power Management function
was incorrectly printed in the output of capability "list".
The value is also printed in the detail output and it has no bug.
- Cleanup pci_conf_print_caplist. Use table. The reason why it loops twice
  is that some capabilities appear multiple times (e.g. HyperTransport cap).
- Print the specification revision of Power Management and AGP not in
  the capability list part but in the detail part.
 Add some HyperTransport related defines. It's required for the MSI.
Pull up following revision(s) (requested by msaitoh in ticket #313):
	sys/arch/amd64/amd64/db_disasm.c: revision 1.20
	sys/arch/i386/i386/db_disasm.c: revision 1.41
	sys/arch/i386/i386/db_disasm.c: revision 1.42
	sys/arch/i386/i386/db_disasm.c: revision 1.43
	sys/arch/i386/i386/db_disasm.c: revision 1.44
	sys/arch/amd64/amd64/db_disasm.c: revision 1.17
	sys/arch/amd64/amd64/db_disasm.c: revision 1.18
	sys/arch/amd64/amd64/db_disasm.c: revision 1.19
KNF. No binary change.
No functional change.
- 0 -> NULL
- Don't use cast.
- Style fix.
- Fix typos in comment.
Fix bugs:
- aaa and daa were reversed. Same as *BSDs.
- fix operand order of shld and shrd. Same as *BSDs.
Add support for sysenter, sysexit, vmptrld, vmptrst and getsec.
Pull up following revision(s) (requested by maxv in ticket #314):
	sys/compat/netbsd32/netbsd32_compat_30.c: revision 1.31
User-triggerable kmem_alloc(0).
Ok martin@ christos@
User
Tickets #309 - #314