posix_fadvise: handle 2 variants for SYSCALL_ALIGN_64BIT

arm/powerpc/xtensa pass @advice as 2nd arg to syscall (vs. canonical 4th)

Current code however does this for UCLIBC_SYSCALL_ALIGN_64BIT (which
powerpc/xtensa) happen to define.

This is not true for ARCv2 ISA and possibly other arch of future which
uses the standard syscall handler in kernel despite 64-bit even register
requirement.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARCv2: Enforce 64-bit data aligned to even register constraint

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>