pass the tests on modelsim
meet all timing constraint at 200MHz
change LDIL (core)
change some signal name
Merge remote-tracking branch 'origin/developer' into emak

Merge remote-tracking branch 'origin/developer' into emak
pass fib_rec.s on modelsim
contains I/O bugs
revert for bug fix
Merge branch 'emak' into developer
Merge branch 'wtr816' into developer
restore init_globals
edit cw3c