fixing/silencing GCC warnings

Signed-off-by: moddingg33k <moddingg33k@t-online.de>
fixing 'make headers_check' error messages

Signed-off-by: moddingg33k <moddingg33k@t-online.de>
acpuclock-7627.c: fixing table selection in select_freq_plan()

In the function 'select_freq_plan()' there's a check to select
the correct table for 1008Mhz CPU's, because there's a conflict
between 7627AA and 8625 chips.

However this check is wrong:
	if (pll_mhz[ACPU_PLL_2] == 245)

It should be:
	if (pll_mhz[ACPU_PLL_1] == 245)

We don't want to check PLL_2 but PLL_1 being '245' or not.

Due of this bug the wrong frequency table is getting selected
for 1GHz 8625 chips with PLL_2=245.

Previously-detected-by: Peter Jung <peter.jung@lge.com>
Signed-off-by: moddingg33k <moddingg33k@t-online.de>
block: *fixing CAF merge derp*

CAF did apply following patches:

2012-02-08: "block: separate out blk_rq_merge_ok() and blk_try_merge() from elevator functions" (https://www.codeaurora.org/cgit/quic/la/kernel/msm/commit/block/elevator.c?h=msm-3.4&id=050c8ea80e3e90019d9e981c6a117ef614e882ed)

After that they applied:

2012-05-24: "block: ioctl support for sanitize in eMMC 4.5" (https://www.codeaurora.org/cgit/quic/la/kernel/msm/commit/block/elevator.c?h=msm-3.4&id=73937f5face75e05ec2a72966d04f4e20aa18379)
(this commit if faulty already after the commit from 2012-02-08!)

And then they merged:

2012-06-07: "Merge commit 'AU_LINUX_ANDROID_ICS.04.00.04.00.126' into msm-3.4" (https://www.codeaurora.org/cgit/quic/la/kernel/msm/commit/block/elevator.c?h=msm-3.4&id=f132c6cf77251e011e1dad0ec88c0b1fda16d5aa)
(this totally screwed the patch from 2012-02-08)

Now it's fixed and like it's supposed like :-)

Signed-off-by: moddingg33k <moddingg33k@t-online.de>
drivers/bluetooth: ADD Kconfig entries for BTLA & BLUEZ
kernel/module.c: *HACK*: enforce loading of ar6000.ko & cfg80211.ko

...no matter which source they came from

(currently this does the trick for being able to use pre-built ATH6KL wifi modules)

Signed-off-by: moddingg33k <moddingg33k@t-online.de>
scripts: revert build host masking

Signed-off-by: moddingg33k <moddingg33k@t-online.de>
FIX: driver core: move the deferred probe pointer into the private area

(moddingg33k): 'INIT_LIST_HEAD(&dev->deferred_probe);' should not exist
		any longer in 'void device_initialize()' after this patch.

		--> So let's remove it.

Nothing outside of the driver core needs to get to the deferred probe
pointer, so move it inside the private area of 'struct device' so no one
tries to mess around with it.

Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
refactoring -> drivers: power: Detect device suspend/resume lockup and log event in pstore

    Rather than hard-lock the kernel, dump the suspend/resume thread stack and
    panic() to capture a message in pstore when a driver takes too long to
    suspend/resume. Default suspend/resume watchdog timeout is set to 12
    seconds to be longer than the usbhid 10 second timeout, but could be
    changed at compile time.

    Exclude from the watchdog the time spent waiting for children that
    are resumed asynchronously and time every device, whether or not they
    resumed synchronously.

    This patch is targeted for mobile devices where a suspend/resume lockup
    could cause a system reboot. Information about failing device can be
    retrieved in subsequent boot session by mounting pstore and inspecting
    the log. Laptops with EFI-enabled pstore could also benefit from
    this feature.

    The hardware watchdog timer is likely suspended during this time and
    couldn't be relied upon. The soft-lockup detector would eventually tell
    that tasks are not scheduled, but would provide little context as to why.
    The patch hence uses system timer and assumes it is still active while the
    devices are suspended/resumed.

    This feature can be enabled/disabled during kernel configuration.

    Cc: Android Kernel Team <kernel-team@android.com>
    Cc: Colin Cross <ccross@android.com>
    Cc: Todd Poynor <toddpoynor@google.com>
    Cc: San Mehat <san@google.com>
    Original-author: San Mehat <san@google.com>
    Signed-off-by: Benoit Goby <benoit@android.com>
    [zoran.markovic@linaro.org: Changed printk(KERN_EMERG,...) to pr_emerg(...),
    tweaked commit message. Moved call to dpm_wd_set() before device_lock() in
    device_resume(). Minor changes to add compile-time inclusion of the feature.
    Renamed 'dpm_wd...' to 'dpm_watchdog...'.]
    Signed-off-by: Zoran Markovic <zoran.markovic@linaro.org>
drivers/cpufreq: conservative: simplify SAMPLING_TIME determination for ARM

...because simple things can be good things, too.

This commit introduces MIN_SAMPLING_RATE & DEF_SAMPLING_RATE
which are used to directly set the driver's minimum and default
sampling rate rather than doing any calculation before.

Signed-off-by: moddingg33k <moddingg33k@t-online.de>
compiler-gcc.h: Add gcc-recommended GCC_VERSION macro

commit 3f3f8d2f48acfd8ed3b8e6b7377935da57b27b16 upstream.

Throughout compiler*.h, many version checks are made.  These can be
simplified by using the macro that gcc's documentation recommends.
However, my primary reason for adding this is that I need bug-check
macros that are enabled at certain gcc versions and it's cleaner to use
this macro than the tradition method:

  #if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ => 2)

If you add patch level, it gets this ugly:

  #if __GNUC__ > 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ > 2 || \
      __GNUC_MINOR__ == 2 __GNUC_PATCHLEVEL__ >= 1))

As opposed to:

  #if GCC_VERSION >= 40201

While having separate headers for gcc 3 & 4 eliminates some of this
verbosity, they can still be cleaned up by this.

See also:

  http://gcc.gnu.org/onlinedocs/cpp/Common-Predefined-Macros.html

Signed-off-by: Daniel Santos <daniel.santos@pobox.com>
Acked-by: Borislav Petkov <bp@alien8.de>
Acked-by: David Rientjes <rientjes@google.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Joe Perches <joe@perches.com>
Cc: Josh Triplett <josh@joshtriplett.org>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Cc: Qiang Huang <h.huangqiang@huawei.com>
Cc: Li Zefan <lizefan@huawei.com>
Cc: Jianguo Wu <wujianguo@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
compiler/gcc4: Add quirk for 'asm goto' miscompilation bug

commit 3f0116c3238a96bc18ad4b4acefe4e7be32fa861 upstream.

Fengguang Wu, Oleg Nesterov and Peter Zijlstra tracked down
a kernel crash to a GCC bug: GCC miscompiles certain 'asm goto'
constructs, as outlined here:

  http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670

Implement a workaround suggested by Jakub Jelinek.

Reported-and-tested-by: Fengguang Wu <fengguang.wu@intel.com>
Reported-by: Oleg Nesterov <oleg@redhat.com>
Reported-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Suggested-by: Jakub Jelinek <jakub@redhat.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
[hq: Backported to 3.4: Adjust context]
Signed-off-by: Qiang Huang <h.huangqiang@huawei.com>
Cc: Li Zefan <lizefan@huawei.com>
Cc: Jianguo Wu <wujianguo@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
ARM: 7421/1: bpf_jit: BPF_S_ANC_ALU_XOR_X support

  JIT support for the XOR operation introduced by the commit
  ffe06c17afbb.

  Signed-off-by: Mircea Gherzan <mgherzan@gmail.com>
  Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

filter: add XOR operation

  Add XOR instruction fo BPF machine. Needed for computing packet hashes.

  Signed-off-by: Jiri Pirko <jpirko@redhat.com>
  Signed-off-by: David S. Miller <davem@davemloft.net>
ARM: 7446/1: spinlock: use ticket algorithm for ARMv6+ locking implementation

	Ticket spinlocks ensure locking fairness by introducing a FIFO-like
	nature to the granting of lock acquisitions and also reducing the
	thundering herd effect when spinning on a lock by allowing the cacheline
	to remain in a shared state amongst the waiting CPUs. This is especially
	important on systems where memory-access times are not necessarily
	uniform when accessing the lock structure (for example, on a
	multi-cluster platform where the lock is allocated into L1 when a CPU
	releases it).

	This patch implements the ticket spinlock algorithm for ARM, replacing
	the simpler implementation for ARMv6+ processors.

	Reviewed-by: Nicolas Pitre <nico@linaro.org>
	Signed-off-by: Will Deacon <will.deacon@arm.com>
	Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7484/1: Don't enable GENERIC_LOCKBREAK with ticket spinlocks

	Now that ARM has implemented its spinlocks with tickets we don't
	need to use the generic lockbreak algorithm. Remove the Kconfig
	from ARM so that we use the arch_spin_is_contended() definition
	from the asm header. This also saves a word in each lock because
	we don't need the break_lock member anymore.

	Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
	Acked-by: Will Deacon <will.deacon@arm.com>
	Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7447/1: rwlocks: remove unused branch labels from trylock routines

      The ARM arch_{read,write}_trylock implementations include unused
      backwards branch labels, since we don't retry the locking operation
      if the exclusive store fails.

      This patch removes the labels.

      Acked-by: Nicolas Pitre <nico@linaro.org>
      Signed-off-by: Will Deacon <will.deacon@arm.com>
      Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7632/1: spinlock: avoid exclusive accesses on unlock() path

      When unlocking a spinlock, all we need to do is increment the owner
      field of the lock. Since only one CPU can be performing an unlock()
      operation for a given lock, this doesn't need to be exclusive.

      This patch simplifies arch_spin_unlock to use non-exclusive accesses
      when updating the owner field of the lock.

      Signed-off-by: Will Deacon <will.deacon@arm.com>
      Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7749/1: spinlock: retry trylock operation if strex fails on free lock

      An exclusive store instruction may fail for reasons other than lock
      contention (e.g. a cache eviction during the critical section) so, in
      line with other architectures using similar exclusive instructions
      (alpha, mips, powerpc), retry the trylock operation if the lock appears
      to be free but the strex reported failure.

      Reported-by: Tony Thompson <anthony.thompson@arm.com>
      Signed-off-by: Will Deacon <will.deacon@arm.com>
      Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7811/1: locks: use early clobber in arch_spin_trylock

      The res variable is written before we've finished with the input
      operands (namely the lock address), so ensure that we mark it as `early
      clobber' to avoid unintended register sharing.

      Signed-off-by: Will Deacon <will.deacon@arm.com>
      Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7812/1: rwlocks: retry trylock operation if strex fails on free lock

      Commit 15e7e5c1ebf5 ("ARM: 7749/1: spinlock: retry trylock operation if
      strex fails on free lock") modifying our arch_spin_trylock to retry the
      acquisition if the lock appeared uncontended, but the strex failed.

      This patch does the same for rwlocks, which were missed by the original
      patch.

      Signed-off-by: Will Deacon <will.deacon@arm.com>
      Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: locks: prefetch the destination word for write prior to strex

      The cost of changing a cacheline from shared to exclusive state can be
      significant, especially when this is triggered by an exclusive store,
      since it may result in having to retry the transaction.

      This patch prefixes our {spin,read,write}_[try]lock implementations with
      pldw instructions (on CPUs which support them) to try and grab the line
      in exclusive state from the start. arch_rwlock_t is changed to avoid
      using a volatile member, since this generates compiler warnings when
      falling back on the __builtin_prefetch intrinsic which expects a const
      void * argument.

      Acked-by: Nicolas Pitre <nico@linaro.org>
      Signed-off-by: Will Deacon <will.deacon@arm.com>

ARM: 7955/1: spinlock: ensure we have a compiler barrier before sev

      When unlocking a spinlock, we require the following, strictly ordered
      sequence of events:

	      <barrier>	/* dmb */
	      <unlock>
	      <barrier>	/* dsb */
	      <sev>

      Whilst the code does indeed reflect this in terms of the architecture,
      the final <barrier> + <sev> have been contracted into a single inline
      asm without a "memory" clobber, therefore the compiler is at liberty to
      reorder the unlock to the end of the above sequence. In such a case,
      a waiting CPU may be woken up before the lock has been unlocked, leading
      to extremely poor performance.

      This patch reworks the dsb_sev() function to make use of the dsb()
      macro and ensure ordering against the unlock.

      Cc: <stable@vger.kernel.org>
      Reported-by: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: Will Deacon <will.deacon@arm.com>
      Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: 7495/1: mutex: use generic atomic_dec-based implementation for ARMv6+

Commit a76d7bd96d65 ("ARM: 7467/1: mutex: use generic xchg-based
implementation for ARMv6+") removed the barrier-less, ARM-specific
mutex implementation in favour of the generic xchg-based code.

Since then, a bug was uncovered in the xchg code when running on SMP
platforms, due to interactions between the locking paths and the
MUTEX_SPIN_ON_OWNER code. This was fixed in 0bce9c46bf3b ("mutex: place
lock in contended state after fastpath_lock failure"), however, the
atomic_dec-based mutex algorithm is now marginally more efficient for
ARM (~0.5% improvement in hackbench scores on dual A15).

This patch moves ARMv6+ platforms to the atomic_dec-based mutex code.

Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: 7668/1: fix memset-related crashes caused by recent GCC (4.7.2) optimizations

Recent GCC versions (e.g. GCC-4.7.2) perform optimizations based on
assumptions about the implementation of memset and similar functions.
The current ARM optimized memset code does not return the value of
its first argument, as is usually expected from standard implementations.

For instance in the following function:

void debug_mutex_lock_common(struct mutex *lock, struct mutex_waiter *waiter)
{
	memset(waiter, MUTEX_DEBUG_INIT, sizeof(*waiter));
	waiter->magic = waiter;
	INIT_LIST_HEAD(&waiter->list);
}

compiled as:

800554d0 <debug_mutex_lock_common>:
800554d0:       e92d4008        push    {r3, lr}
800554d4:       e1a00001        mov     r0, r1
800554d8:       e3a02010        mov     r2, #16 ; 0x10
800554dc:       e3a01011        mov     r1, #17 ; 0x11
800554e0:       eb04426e        bl      80165ea0 <memset>
800554e4:       e1a03000        mov     r3, r0
800554e8:       e583000c        str     r0, [r3, #12]
800554ec:       e5830000        str     r0, [r3]
800554f0:       e5830004        str     r0, [r3, #4]
800554f4:       e8bd8008        pop     {r3, pc}

GCC assumes memset returns the value of pointer 'waiter' in register r0; causing
register/memory corruptions.

This patch fixes the return value of the assembly version of memset.
It adds a 'mov' instruction and merges an additional load+store into
existing load/store instructions.
For ease of review, here is a breakdown of the patch into 4 simple steps:

Step 1
======
Perform the following substitutions:
ip -> r8, then
r0 -> ip,
and insert 'mov ip, r0' as the first statement of the function.
At this point, we have a memset() implementation returning the proper result,
but corrupting r8 on some paths (the ones that were using ip).

Step 2
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 1:

save r8:
-       str     lr, [sp, #-4]!
+       stmfd   sp!, {r8, lr}

and restore r8 on both exit paths:
-       ldmeqfd sp!, {pc}               @ Now <64 bytes to go.
+       ldmeqfd sp!, {r8, pc}           @ Now <64 bytes to go.
(...)
        tst     r2, #16
        stmneia ip!, {r1, r3, r8, lr}
-       ldr     lr, [sp], #4
+       ldmfd   sp!, {r8, lr}

Step 3
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 0:

save r8:
-       stmfd   sp!, {r4-r7, lr}
+       stmfd   sp!, {r4-r8, lr}

and restore r8 on both exit paths:
        bgt     3b
-       ldmeqfd sp!, {r4-r7, pc}
+       ldmeqfd sp!, {r4-r8, pc}
(...)
        tst     r2, #16
        stmneia ip!, {r4-r7}
-       ldmfd   sp!, {r4-r7, lr}
+       ldmfd   sp!, {r4-r8, lr}

Step 4
======
Rewrite register list "r4-r7, r8" as "r4-r8".

Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: 7670/1: fix the memset fix

Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by
recent GCC (4.7.2) optimizations") attempted to fix a compliance issue
with the memset return value.  However the memset itself became broken
by that patch for misaligned pointers.

This fixes the above by branching over the entry code from the
misaligned fixup code to avoid reloading the original pointer.

Also, because the function entry alignment is wrong in the Thumb mode
compilation, that fixup code is moved to the end.

While at it, the entry instructions are slightly reworked to help dual
issue pipelines.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Alexander Holler <holler@ahsoftware.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: 7674/1: smp: Avoid dummy clockevent being preferred over real hardware clock-event

With recent arm broadcast time clean-up from Mark Rutland, the dummy
broadcast device is always registered with timer subsystem. And since
the rating of the dummy clock event is very high, it may be preferred
over a real clock event.

This is a change in behavior from past and not an intended one. So
reduce the rating of the dummy clock-event so that real clock-event
device is selected when available.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: 7822/1: add workaround for ambiguous C99 stdint.h types

The C99 types uintXX_t that are usually defined in 'stdint.h' are not as
unambiguous on ARM as you would expect. For the types below, there is a
difference on ARM between GCC built for bare metal ARM, GCC built for glibc
and the kernel itself, which results in build errors if you try to build with
-ffreestanding and include 'stdint.h' (such as when you include 'arm_neon.h'
in order to use NEON intrinsics)

As the typedefs for these types in 'stdint.h' are based on builtin defines
supplied by GCC, we can tweak these to align with the kernel's idea of those
types, so 'linux/types.h' and 'stdint.h' can be safely included from the same
source file (provided that -ffreestanding is used).

                   int32_t         uint32_t               uintptr_t
bare metal GCC     long            unsigned long          unsigned int
glibc GCC          int             unsigned int           unsigned int
kernel             int             unsigned int           unsigned long

Acked by: Dave Martin <dave.martin@arm.com>

Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: 7990/1: asm: rename logical shift macros push pull into lspush lspull

Renames logical shift macros, 'push' and 'pull', defined in
arch/arm/include/asm/assembler.h, into 'lspush' and 'lspull'.
That eliminates name conflict between 'push' logical shift macro
and 'push' instruction mnemonic. That allows assembler.h to be
included in .S files that use 'push' instruction.

Suggested-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>