libmp: A preliminary step om the way to a barrier.
simulator: handle diverging stack cache content and stack cache pointers
hardware: Insert timescale into generated code for simulation.
hardware: Tweaks for SRAM controller.
hardware: Initial version of QDRII+ memory controller.
config: Initial configuration for Stratix V development kit.
config: Remove "ports" tags from configuration files.
hardware: Synthesize with a bit more effort for DE2-70 board.
bootloader: Cleaner code in CMP slave.
hardware, simulator, doc: Support for invalidation of data and method cache.
Stratix V board: config files, top level and quartus project files added for the Stratix V development board and IO add-on board.
merge: Merged master into mp_barrier and added some files.
Corethread: corethread create, join and exit are implemented and a test is added.
libraries: libmp and libcorethread are now running.
libmp: mp_broadcast() added.
libmp: shared memory barrier implemented and noc barrier fixed.
c: WCET optimizations.
Merge branch 'master' into mp_barrier
c: benchmark added and library code optimized for worstcase.
Merge branch 'master' into mp_barrier