msm8974: Increase size of audio region for ION

 * Needed for 5.1 AAC playback

Change-Id: I85a9d37f65fad46718e27c9c83f6e09dbf74f02e
ARM: dts: msm: Add support for second qcrypto device for 8974

Add entry for a second qcrypto instance that uses a different
pipe pair for data transfer to/from CE hardware. This will allow
clients to use different PIPE key register set intended for a
different use case.

Change-Id: Ibdf5ae10de63f1a26ce37ab9b74e4a60346cc105
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
ARM: dts: msm: BIMC for 8974 class devices

Map memory for tools to access BIMC facilities.

Change-Id: I4f3286f4aae47e181d7cde3f303a4ca995b5da52
Acked-by: rahul ramasubramanian <rahulr@qti.qualcomm.com>
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
mmc: block: Backport HS400 changes from 3.10

mmc: block: Remove call to mmc_blk_set_blksize

It no longer exists.

CRs-Fixed: 561382
Change-Id: I1ca5e8f93241264ed9ffdce53067cb16476c1c66
Signed-off-by: Arve Hjønnevåg <arve@android.com>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>

mmc: core: add deferred resume support

This patch enables the deferred resume support which would
prevent initialization of the card each time the system resumes.
With this change, the resume process would only be initiated if
a request is received.

Following scenario can occur:
1. device runtime suspended, system suspend is triggered
   When resumed, the device would not be resumed until a
   request is received.
2. device is runtime active, system suspend is triggered
   When resumed, the device would be marked as BUS_NEEDS_RESUME
   and actual resume would happen, when a request is received.
   At this point, the device may also enter runtime-suspend or
   system suspend may also occur. In both the cases, since the
   device has not been resumed, it won't be suspended again.
   However, the platform device would be runtime suspended
   and resumed as before.
   It can so happen that the card is removed even before a
   request is received. In this case the device would be
   resumed and card would be removed from core layer and
   upper layers would be notified.
In case of SDIO cards, this change would not have any effect
since manual resume would be enabled for devices supporting
a block read/write commands.

CRs-Fixed: 561382
Change-Id: Id39befea109ee24864dfde0898395b972d0a1b3a
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>

ARM: dts: msm: Add HS400 support to SDHC1 for MSM8974Pro

Add device tree entries to enable HS400 support for SDHC1 instance on
MSM8974Pro platform.

CRs-fixed: 613318
Change-Id: I1284cf22b1f57c0d3ba43ab21cafb9ffcdccd237
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>

ARM: dts: msm8974: Update MPM mapping to bypass uart_2_irq

Include uar_2_irq in bypass list to allow XO shutdown as this
is not wakeup-capable. uart driver has wakeup gpio on CTS pin and
optional wakeup gpio on rx pin. This should take care of wakeup
from low power state if there is any activity on the pin.

Change-Id: I10d2347eb760146b69f5b13f4cababbfcadb17bf
Signed-off-by: Girish Ghongdemath <girishsg@codeaurora.org>

mmc: sdhci-msm: add default qos

If cpu-dma-latency is not defined in dts files, set it
to 200usec

Change-Id: I27b0357b4d88842a258332250bae66efac3ee5e2
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>

mmc: sdhci-msm: improve tuning process

In newer hardware, the tuning process is not able to always
find a reliable phase to use for sampling data. This is mostly
due to hardware. This problem manifests itself as all successful
tuning phases, which means that the phase choosen could be a bad
one but is not identified as such at the time of tuning. So in
order to work around this, rely on optional drive types implemented
by the eMMC card, in addition to the mandatory drive type (50 ohm).

By using drive types supported by the card, when all phases are
sucessful in tuning, change drive type to a different value in the
list of supported drive types and retune. This will continue for all
tuning phases until a valid one is found. After that the drive type
is reset to the default one, if changed.

Change-Id: I348fb30daa43d97c58f83f7e4a22019f94ef4954
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>

ARM: dts: msm: Update bus bandwidth votes for sdhci on 8974

Some versions of 8974 supports eMMC HS400 mode providing maximum
throughput of 400MB/s. Update the list of bus bandwidth votes to
make sure appropriate vote is placed in this mode.

Change-Id: I5e3bed70d8c8c1c6423483f7469849823e3ebb2c
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>

mmc: core: get drive types supported by eMMC cards

Get the various drive types other than the default supported
by the card.

Change-Id: I122971e4fb4a3ab98f0078ceafca3380e9c0e2d1
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>

x9007: Enable HS400 support

Change-Id: If085aa179f588293c1ca4a5d20c9c925cd2830b6

mmc: sdhci: finish the request if sdhc is in bad state

In the current code, if sdhci_check_state returns true a tasklet is
scheduled which doesn't complete the request if host->mrq is NULL,
which is the case, if sdhci is in bad state. This would make the
mmcqd thread wait for completion infinitely.
Hence, complete the request if sdhci_check_state returns true instead
of scheduling the tasklet.

CRs-Fixed: 615537
Change-Id: I8e2950c3999ac3806f9d631c52d86f0dc13b992f
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>

mmc: core: fix the issue with clock scaling in HS400 mode

Clock scaling feature would scale up/down the MMC interface clock
frequency based on the load on storage. During clock scale up in HS400
bus speed mode, SW is unncesserily doing the tuning even after HS400
switch is done. This change fixes this bug.

Change-Id: Ica39acc41b14095438a7ccf536c3c7e5792d9c41
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

mmc: core: Fix runtime suspend/resume issue during mmc_blk_probe() failure

During card detection within mmc_rescan(), mmc_rpm_hold() will be called
on host->class_dev before initializing the card and shall be released
after card detection. During card detection, once the card device is
added, MMC block driver probe gets called and in case that probe fails
due to block read/write cmd error, then the block driver marks that card
as removed. Later when mmc_rpm_release() is called within mmc_rescan(),
the runtime suspend of host->class_dev will be invoked immediately. The
commands that are sent during runtime would fail with -ENOMEDIUM and if we
propagate the same to rpm framework, the runtime suspend/resume for this
device will never be invoked even if the card is detected fine later on
during subsequent removal and insertion. Hence, do not report this error to
upper layers.

Change-Id: I9e60e9fb4ebc3d267cedae14aa88021000311427
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>

mmc: sdhci: Add support for auto-calibration

This patch adds Programmable Delay Line auto-calibration
support if supported by respective hosts.If the host
supports auto-calibration this change would enable
sending CMD19/CMD21 before any read operation.

CRs-Fixed: 516314
Change-Id: I8a0f51206dc0e174519dd71f0c75267a9e08e7f7
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>

mmc: sdhci: clear interrupt status during controller reset

In some cases, it is possible that the hardware might trigger
an interrupt just about the same time the software tries to
reset the controller. In such case, the hardware interrupt will
be handled after the current thread release spin lock. This leads
to spurious interrupt handling after the completion of reset.

Change-Id: I75211adee1179b0636a918f5ceb68a072ad02a6c
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>

mmc: sdhci-msm: dump vendor specific registers during error

Implement dump_vendor_registers host operation to print the
vendor specific registers in addition to standard SDHC
register during error conditions.

Change-Id: I347e8f0373264574a80e460967afba6859607ac9
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>

mmc: sdhci-msm: Enable auto-calibration using auto-cmd21

This patch enables automatic calibration for eMMC devices
in using auto-command21. This feature is disabled by default
and can be enabled using the sysfs attribute
'enable_auto_cmd21'.

CRs-Fixed: 516314
Change-Id: I020c61cb9dee56c0ebe37864e67e4753ddee1adc
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>

mmc: sdhci-msm: Cancel disabling AHB bus transfer

The SDCC5 controller and later revisions can handle reset in middle of
an ongoing transfer without the need to disable AHB bus transaction
separately. Disable the workaround for the newer revisions of the core.

Change-Id: I825bff8cccfc3084af9bbbf67a241bb73647872f
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>

mmc: sdhci-msm: ignore data-end-bit error in 1 bit mode

Some SDHC controllers are unable to handle data end-bit
errors in one bit mode.
This patch adds a quirk to ignore data-end-bit error in
1-bit mode in Qualcomm SDHC controllers.

Change-Id: Ica0f10573d654021449c32197b126e12bb1a3c10
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>

mmc: sdhci-msm: Fix incorrect flags passed during spin_unlock_irqrestore

Fix following bug -

foo_bar1(int arg1, unsigned long flags) {
	spin_unlock_irqrestore(lock, flags); // step 1
	<do something>;
	spin_lock_irqsave(lock, flags); // step 2
}

foo_bar() {
	unsinged long flags;
	spin_lock_irqsave(lock, flags); // step 3
	foo_bar1(arg1, flags);
	spin_unlock_irqrestore(lock, flags); // step 4
}

The "flags" might be changed in step 4 due to irqrestore and irqsave
in foo_bar1().

Change-Id: I42366f7acdde022705f4b3dd06122d54ad817078
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>

mmc: sdhci: Enhance debug register dump

Add new host operation dump_vendor_regs to provide a
mechanism through which host drivers can dump vendor
specific registers in addition to SDHC registers
during error conditions.

Change-Id: Ifba3ddcb18c3c0917343d99fe58d5ed04b2da871
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>

mmc: sdhci-msm: add sdio wakeup support

This patch adds the sdio wakeup funtionality in either of the
two methods:

1. If a dedicated mpm interrupt is present in the particular
   slot, it is configured to be used as wakeup.

2. If dedicated mpm interrupt is absent for a slot, then
   DAT1 line gpio is configured as wakeup.

Change-Id: Ide54f807c12262429011e245de7dcecadcc60f3b
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>

ARM: dts: msm: add SDHC DAT1 line wakeup support for 8974

This patch adds mpm and gpio based wakeup interrupt support.
SDIO card interrupt can wake up the system by pulling the
DAT1 line low. When the system is suspended mpm monitors
this line and wakes up the system.

Change-Id: I4ea5e29200e7138bca18ed429175a39414ea3318
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>

mmc: quirks: enable clock gating for AR6004 card

This patch whitelists the AR6004 card for clock-gating.
The controller supports asynchronous interrupt functionality
which enables to receive interrupts from the card when clocks
are off. Hence, clocks can be turned off when idle.

This patch whitelists the card, to let the clock-gating
framework gate the clock during idle time.

Change-Id: I651f86e42595cc82f99093c06ee220a1d0ec95a9
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>

msm: clock-8974: Update SDCC1 Apps clock frequency for MSM8974Pro

Update SDCC1 Apps clock frequency for MSM8974Pro to match latest software
frequency plan.

CRs-fixed: 613318
Change-Id: Id88259998862aade7492f1b56592e68beda6fd17
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>

mmc: sdhci: introduce sdhci_update_clock helper to re-enable clock

There are three places where same piece of code is used. Let's split it
to a separate function.

Change-Id: Ie7a76b01ad5545c616a806ba24ef301abcc88dab
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Chris Ball <cjb@laptop.org>

mmc: sdhci: Fix possible spec. violation during voltage switch sequence

With commit 0797e5f145 (mmc: core: Fixup signal voltage switch), voltage
switch sequence for UHS-I cards is broken if used with sdhci driver.
The commit expects the SD clock to be disabled when mmc_set_ios() is
issued but sdhci_do_set_ios() re-enables the SD clock for few cycles
after disabling which is a specification violation during voltage
switch sequence. This failure is observed only for a small group of
cards where they ultimately fall-back into high-speed mode even if
UHS-I modes are supported.

Change-Id: Ie275326627a84bfcd4352637a043296c01c175a6
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>

mmc: sdhci: Introduce new flag SDHCI_USING_RETUNING_TIMER

Add a new flag of SDHCI_USING_RETUNING_TIMER to represent if the host
is using a retuning timer for the card inserted.

This flag is set when the host does tuning the first time for the card
and the host's retuning mode is 1. This flag is used afterwards whenever
needs to decide if the host is currently using a retuning timer.

This flag is cleared when the card is removed in sdhci_reinit.

The set/clear of the flag and the start/stop of the retuning timer is
associated with the card's init/remove time, so there is no need to
touch it when the host is to be removed as at that time the card should
have already been removed.

Change-Id: I47caa8854429f57dc9e139a9817fda6c501d9441
Signed-off-by: Aaron Lu <aaron.lu@amd.com>
Reviewed-by: Girish K S <girish.shivananjappa@linaro.org>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>

mmc: sdhci: enhance preset value function

4d55c5a1 ("mmc: sdhci: enable preset value after uhs initialization")
added preset value support and enabled it by default during sd card init.

Below are the enhancements introduced by this patch:

1. In current code, preset value is enabled after setting clock finished,
which means the clock is manually set by driver firstly and then suddenly
switched to preset value at this point. So the first setting is useless
and unnecessary. What's more, the first clock setting may differ from the
preset one.  The better way is enable preset value just after switch to
UHS mode so the preset value can take effect immediately. So move preset
value enable from mmc_sd_init_card to sdhci_set_ios which will be called
during set timing.

2. In current code, preset value is disabled at the beginning of
mmc_attach_sd.  It's too late since low freq (400khz) should be set in
mmc_power_up.  So move preset value disable to sdhci_set_ios which will
be called during power up.

3. host->clock and ios->drv_type should also be updated according to the
preset value if it's enabled. Current code missed this.

4. This patch also introduce a quirk to disable preset value in case
preset value doesn't work.

This patch has been verified on sdhci-pxav3 platform with both preset
enabled and disabled.

Change-Id: Ib77f09ecadc9ba033f14687948c6fbf40f59f83f
Signed-off-by: Kevin Liu <kliu5@marvell.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <cjb@laptop.org>

mmc: sdhci-msm: set dma mask for lpae/64-bit machines

On machines that support more than 32-bit address via lpae or 64-bit buses
set the dma mask as 64-bit.

Change-Id: Ida88f3999fd5e7d09ebe73bb3481d3f1f4cf30c2
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>

mmc: sdhci-msm: Add software capabilities for voltage init

With SDCC5 the capabilities register is not advertising the
3.0 voltage features (except for 8974 and 8084).

So add the software capabilities for voltage initialization
for rest of the targets with SDCC5.

CRs-Fixed: 568227
Change-Id: Ida53f5ad7249cd0cd8428b4839dfd932b04e31fa
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>

mmc: sdhci: retune on cmd or data CRC error

Initiate a DLL (delay locked loop) retune for the next command,
if the current command fails with a CRC error.
This may help to choose a different phase (delay) if the same
has changed over the elapsed period of time.

CRs-Fixed: 587985
Change-Id: I21f6a5dadb096dd38d41fcf2251fa50b03c8bbb4
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>

mmc: sdhci: add asynchronous interrupt support for sdio card

Some controllers can gate the clock to save power
even for SDIO cards. In such cases, an asynchronous
interrupt mechanism is used to receive interrupts
even when clocks are off.

This patch wakes up the sdio thread if interrupts
were received when clocks were off.

Change-Id: Ifcfafad251dedc992637596b6bb9349cfbca5d8b
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>

mmc: sdhci: add sdio wakeup event

This patch adds wakeup event capability for sdio cards.
When a wakeup event is received during suspend, a reference
to the card devices' wakeup source is taken for 300 ms.

It is expected that the function driver would act on the
wakeup event within this time-period.

Change-Id: I80fe0c450e8d9b3df51aa181d667d94517c961dc
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>

mmc: sdhci: Use right API to read/write host control2 register

The SDHCI host control2 register offset is 0x3E which is not
word aligned and is only 16 bits wide. But we use readl/writel
to read/write to it. Use readw/writew to avoid any alignment
issues.

Change-Id: Ibaa87ce46f2a2dd97f9e1c7979adb38e426acd5b
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>

mmc: core: add wakeup functionality to sdio cards

This patch initializes wakeup source if the detected card
is a sdio card and enables the wakeup capability.

Platform drivers would have to invoke:
 * pm_wakeup_event on this card device to signal a wakeup
 * corresponding pm_relax have to be invoked

Change-Id: Ic8d5c98073e8ed3f676eb42fc0ce1f13a11cb40f
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>

mmc: sdhci-msm: add USE_CORE_PM capability

Defining this capability would invoke the suspend/resume
routines defined for mmc_host device by the PM framework.

CRs-Fixed: 490021
Change-Id: I6fde407ed91f0a7249923bb156482378e2bb727c
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>

mmc: sdhci-msm: Fix power IRQ issue uncovered in 3.10 kernel

The request to change the VDD I/O voltage level to high/low will
trigger an IRQ only when -

1. SWITCHABLE_SIGNALING_VOLTAGE bit 29 of SDCC_MCI_GENERICS register
is set.
2. Above condition is true and when there is a state change in VDD
bit 3 of SDHCi Host Control 2 register.

Until now, the MMC core layer issues I/O high request only after
the controller is powered up. The I/O high request is same as the reset
state of host control2 register which will never trigger an IRQ. The
driver already handles this case by ensuring that I/O voltage is set
to high as part of power up itself and thus returns immediately when
I/O high request is issued later. But in 3.10 kernel, this request is
issued even before the controller is powered up. Hence, check for
host->pwr state to avoid waiting for an IRQ that never comes.

Change-Id: I31b6723f53397be1ba151305ead89e739560eb20
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>

mmc: sdhci-msm: Add software capabilities for 8-bit slot

With SDCC5 the capabilities register is not advertising the
8-bit capability feature (except for 8974 and 8084).

So add the software capabilities for 8-bit slot for rest of
the targets with SDCC5.

Change-Id: I288292f37d77507bf5aaa44bf156496b4df87234
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>

Conflicts:
	arch/arm/boot/dts/msm8974pro-ab-pm8941-x9007.dts
	drivers/mmc/core/mmc.c
	drivers/mmc/host/sdhci-msm.c