edp: core: add new gpu high threshold for high core profile

Add new gpu high threshold for high core profile, this value
need to be tuned during edp tuning.

Bug 1329643

Change-Id: I77fff3a62c8796f7512cfb6e0c79cbae46d616d4
Signed-off-by: Rick Song <ricks@nvidia.com>
Reviewed-on: http://git-master/r/261874
Reviewed-by: Vandana Bansal <vandanab@nvidia.com>
Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com>
Tested-by: Venkata (Muni) Anda <vanda@nvidia.com>
GVS: Gerrit_Virtual_Submit
mmc: sdhci: Use quirks2 for defining new quirks

Revert back quirks to 32 bits long and use quirks2 to define any new
required quirks.

Bug 1330567

Change-Id: I5e7095fb18b2ccd19df44338e42b2a69d94be787
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/260564
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
GVS: Gerrit_Virtual_Submit
media:video:tegra: ov5693 using real gain mode

Current OV5693 gain mode is sensor gain. sensor gain mode can't
support 16x gain. so gain mode change to real gain mode.

Bug 1310144

Change-Id: Iaf71983273655c93847b79ebd384020f14b75ff4
Reviewed-on: http://git-master/r/258663
(cherry picked from commit b530ca75905cf10cfb436de78f0130d3d1a13d4b)
Signed-off-by: Karl Kim <kkim@nvidia.com>
Reviewed-on: http://git-master/r/260882
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter Kim <pekim@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Breczinski <pbreczinski@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
crypto: tegra-se:Correct RSA context save sequence

While saving LP0 context, save RSA modulus first and
then RSA exponent

Bug 1346862

Change-Id: I886af12970ddafb4dff3fbcdadca0bbe9dcbaff3
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/261342
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
GVS: Gerrit_Virtual_Submit
ARM: tegra: macallan: update sys EDP tables

(1) Added RBAT LUT for psy depletion & adjusted E-state tables
(2) Added 500mW steps in AP+DRAM E-state table

Bug 1306298

Change-Id: Ic6d5ce7b894d1cdcf3f5667cc939cdf9cde55c81
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/261878
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vandana Bansal <vandanab@nvidia.com>
Tested-by: Vandana Bansal <vandanab@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
GVS: Gerrit_Virtual_Submit
mmc: tegra: Remove chip specific hw_ops

Removed chip specific hw_ops. There really is only one callback being
used currently to handle T30 clock stabilization bug.
Added a quirk2 to handle clock stabilization WAR for T30.
Added nvquirk to selectively enable HS200 capability.

Bug 1330567

Change-Id: I2c2e7a07677c4c4fc7262643ae94537c786110fe
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/260565
GVS: Gerrit_Virtual_Submit
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
mmc: tegra: Clean up chip specific defines

Cleaned all chip specific defines.
Separate SOC data for SDMMC controllers in each chip.
Pass parent clock sources list through soc data. Skip parent selection
if only one parent is available.

Bug 1330567

Change-Id: I6dae169ab69330b22ca3c87658a2f75c53f32a81
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/260566
GVS: Gerrit_Virtual_Submit
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
mmc: tegra: Single function for regulator ops

Use single function for SDMMC related regulator enable, disable and
set voltage operations to avoid repetitive code.

Bug 1330567

Change-Id: Ie93067692090a43c0ac76f5689517bced2aeae58
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/260567
GVS: Gerrit_Virtual_Submit
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
mmc: tegra: Refactor frequency tuning code

Chip specific tuning frequency list.
Support low, high and max frequencies for each chip.
Generic tuning constraints update procedure for better scalability.

Synchronization between multiple devices for setting core voltage
constraints during tuning.
When tuning is being run for any interface, avoid data transfers on all
interfaces that are yet to finish tuning. This would avoid data errors
due to core voltage fluctuations as a result of tuning vcore constraints.

Fixed tuning status update as per the core voltage set status and tuning
window status.

If the verification of an already tuned best tap value fails, force
retuning.

Option to easily configure support for any two frequencies when DFS is
enabled. Simplified procedure to support higher tuning frequency count.

Modularize tuning code for better scalability, maintainability and
readability.

Bug 1330567

Change-Id: I98533a3ceb661b5b54c8903341181ad0009f4dfb
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/260568
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
ARM: tegra: sdhci: Pass boot vcore in plat data

Pass boot core voltage limit through platform data.
Enable nominal voltage tuning support for pluto.

Bug 1330567

Change-Id: Ia1c349bcf22cb80423d0dd782209fd94dc35b507
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/260569
GVS: Gerrit_Virtual_Submit
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
video:tegra:ad5823 support physical/working range

NVCS can't set the full range because the ad5823 driver is
clipping position value as working range.
This is separated physical and working range

Bug 1340766

Change-Id: I61f4dbdc8572fd6b1725a9e0803656b9d0bc1ec4
Reviewed-on: http://git-master/r/259886
(cherry picked from commit fd4453a8ffb35dcca59a079d6e7b5599f7ab4e48)
Signed-off-by: Karl Kim <kkim@nvidia.com>
Reviewed-on: http://git-master/r/261018
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
arm: tegratab: load touch fw according to board revision

Change-Id: Ica93560f8eba67d5ba9975c42e0c7431f1b10ce8
Signed-off-by: David Yu <davyu@nvidia.com>
Reviewed-on: http://git-master/r/244945
Reviewed-by: Gabby Lee <galee@nvidia.com>
(cherry picked from commit 167bb899063afd987bd05f19d57da8a1fd377de9)
Reviewed-on: http://git-master/r/247723
Reviewed-by: Bo Kim <bok@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Robert Collins <rcollins@nvidia.com>
input: touch: maxim: get firmware name from board file

Change-Id: Iab848bb8176d6003d45a8e8650a99de02f9d50b3
Signed-off-by: David Yu <davyu@nvidia.com>
Reviewed-on: http://git-master/r/263260
Reviewed-by: Bo Kim <bok@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Robert Collins <rcollins@nvidia.com>
arm: pluto: power: update core cap table

  - update the table of normal profile.
  - keep gpu throttle at 672 MHZ during using cpu priority,
    for high core profile.
  - move power from cpu to gpu as possible during using
    gpu priority, for high core profile.

Bug 1329643

Change-Id: I01876867823dc92944044aa6974cd35bf8a94e89
Signed-off-by: Rick Song <ricks@nvidia.com>
Reviewed-on: http://git-master/r/261565
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vandana Bansal <vandanab@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
media: video: tegra: IMX135: add non-AOHDR modes

Add the following non-AOHDR modes
4208x3120
2104x1560
1920x1080

Bug 1345012

Change-Id: I0d888de90e6147d95c18206bcf81f4db70c26bb1
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/263567
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yin-Chia Yeh <yyeh@nvidia.com>
Reviewed-by: Sean Pieper <spieper@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
 power: max17048: set wakeup capability

 set the device as wakeup capable and let the user space enable
 to wakeup the system from LP0/Suspend state.

 Bug 1342974

Change-Id: I00946d40a45837a64d2d4b59e3852e2213736cfa
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-on: http://git-master/r/264782
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
ARM: tegra: dalmore/pluto: Enable max freq for SD

Enabling max frequency support for SD cards on Dalmore A05 and
pluto platforms.

Bug 1330567

Change-Id: Ia27604fa2745f6b045ec20d0882f7b196be9f876
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/263812
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
ARM: tegra: dalmore: Enable max freq for SDIO

Enabling max freq support for SDIO on Dalmore A05 platform.

Bug 1330567

Change-Id: If177b605e6db5034eb7e33eaf51b26446274a5dc
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/263813
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
mmc: tegra: Clear tuning overrides if not required

If there is no need to maintain boot voltage, clear tuning
override voltages set.

Bug 1353926

Change-Id: Ie36fd98b6245839ea8ec4b6fd9a2afb4cd56ff3b
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/264940
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
ARM: tegra: macallan sys EDP can lowered to 19W

Needed for stability fixes.

Bug 1306298
Bug 1353057

Change-Id: I6943fd77ae364d2550b75ad5829b5e5beaa888f1
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/265328
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Vandana Bansal <vandanab@nvidia.com>