media: video: tegra: tegra_camera: re-arch power and clock

There are a couple of issues found in tegra_camera.

1. clock enable/disable is controlled by user space.
   -> If client process crashes, there is no way to disable clock.
2. power enable/disable is associated with clock enable.
   -> There is no reason to relate power with clock.
   -> There is only one regulator for this driver.
   -> As same as #1, it may leave power up when client process crashes.
3. driver allows multiple clients to access.
   -> This is not the case for this driver.

This changes addresses the problems described above.

Bug 948780

Change-Id: Ie534771327175f56cf0e138f1c07096ddba470a8
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/92386
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Conflicts:
	drivers/media/video/tegra/tegra_camera.c
video: tegra: dc: add tracing information

add trace_printk to log useful debug information.

Bug 870685

Change-Id: I29c0b1600f234ebb06d19c8b6c713b16f6e7643c
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/89204
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Malani <pmalani@nvidia.com>

Conflicts:
	drivers/video/tegra/dc/dc.c
ARM: tegra2: dvfs: Update DVFS rails statistic for Tegra2

LP2 state of Tegra2 is considered into rail statistic.

Change-Id: Iab2e0fe25ecb8feca1f4aa1040ce5020e6dcf584
Signed-off-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-on: http://git-master/r/98118
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
ARM: tegra: pcie: fix pcie resume issue

Its observed that PCIE all clocks enabled on resume.
Follow up resume and suspend only if any port added

bug 943712

Change-Id: I0644aad8a4994726451cda094f2607eb8398aadf
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/95836
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
ARM: tegra: provide fixed mapping for PCIe host

Provide a fixed mapping for the PCIe host registers. This reduces the pressure
on the VMALLOC area significantly.

bug 969392

Change-Id: I80ea0dd5e81a005f86a26eb47aea00d78e9e0ad2
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/96748
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
ARM: tegra: dc: support YUV422 format

Change-Id: I8aa25b03fe6801882b65209cb1a6e125ef27ac2c
Signed-off-by: Michael I. Gold <gold@nvidia.com>
Reviewed-on: http://git-master/r/98319
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
kernel: nvhost: add OOM checks

This change adds check for out of memory conditions
after memory allocations

Bug 967504

Change-Id: Icafc16528880ea376dd69a023570b85c25e3d057
Signed-off-by: Anton Kondratenko <akondratenko@nvidia.com>
Reviewed-on: http://git-master/r/97113
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

Conflicts:
	drivers/video/tegra/host/nvhost_job.c
arm: tegra: pm: use writel instead pmc_32kwritel

For update of PMC_CTRL register delay is not required.
Replacing pmc_32kwritel by writel to improve cluster switch time.

bug 954247

Change-Id: Ic39c6fafd606321d549cf26e4cfe662f462b9bdc
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/97229
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
power: max17048: configure hibernate mode

configure fuel-gauge to enter and exit hibernate mode

Change-Id: Ifaa471a4b796fc1aa2b30f109091227eb19cf6ae
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/97900
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: cardhu: pm299: off core-power in LP0

Making core power to be off in LP0.

bug 973979

Change-Id: I0c8f44fce2204395530c63fd0056f98a3c4ef115
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/98413
Reviewed-by: Automatic_Commit_Validation_User
ARM: tegra: cardhu: open drain pin need not to set tristate

When open drian pin is set as gpio-input, the pin is set as
tristate and hence need not to set this again tristate from
pinmux controller.
Setting the pin in normal in pinmux controller and then
- setting HIGH by gpio-input and pull-up so that pin is
  tristated through gpio controller.
- Setting LOW by gpio-output and drive to LOW. As pin is in
  normal state in the pinmux, the output will be set to LOW.

bug 973591
bug 969182

Change-Id: Ia9518f79987c9562bb57f95a468bdc5b5e143b87
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/98434
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
ARM: mm: cache-l2x0: use L2X0_CACHE_ID_PART_MASK to get cache-id

l2x0_unlock does not use L2X0_CACHE_ID_PART_MASK to get the
actual cache-id, thus always iterating over only one I and one
D lockdown register.

Change-Id: If473bd32991a6a97f9da6b8712f297a8bd00d32e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/96954
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
video: tegra: dc: Activate register update after programmed

Inform DC register updated after we programmed. This eliminates
the display corruption while device enters and resumes from LP0.

Signed-off-by: Mark Zhang <markz@nvidia.com>

bug 964626

Change-Id: I4c655d4800474c675d4cdb6204d6fe66e8c6c4b5
Reviewed-on: http://git-master/r/98336
Tested-by: Mark Zhang <markz@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peer Chen <pchen@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
asoc: tegra: Add TDM mode support

Added TDM mode support in I2S driver.
Added support functions in AHUB to pass audio/client bits.
Added support functions in AHUB to pass audio/client channels.
Fixed the stopping of I2S/TDM by clearing the fifo.

Bug 948478

Change-Id: I246942b3a07ffcfbcfafbc820208190bd3acc5d4
Signed-off-by: Nitin Pai <npai@nvidia.com>
Reviewed-on: http://git-master/r/98456
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>

Conflicts:
	sound/soc/tegra/tegra30_ahub.h
	sound/soc/tegra/tegra30_i2s.c
hdmi: Set INJECT_NULL_SAMPLE only for stereo streams

Bug 953210

Change-Id: Id40b3fe90174a2a8c9a6faf3f35f61d9f7eeb642
Signed-off-by: Sayak Ghosh Choudhury <sayakc@nvidia.com>
Reviewed-on: http://git-master/r/98477
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
arm: oprofile: backtracing support for Android

The stack frame for Android is slightly different than that used
for vanilla Linux.
Bug 935536

Signed-off-by: Ryan V. Bissell <rbissell@nvidia.com>
Reviewed-on: http://git-master/r/82600
(cherry picked from commit bb6d1e211bdb41c129ee17489814327d7d8d2fb8)

Change-Id: Ie0e924d45398c7def58e3722035911d905614b6f
Reviewed-on: http://git-master/r/89507
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Oleg Strikov <ostrikov@nvidia.com>
Reviewed-by: Janne Hellsten <jhellsten@nvidia.com>
Tested-by: Ryan Bissell <rbissell@nvidia.com>
net: usb: raw-ip: Fix autopm / system suspend issues.

Add system suspend count and avoid urb activity during
system suspend.  Use async autopm to avoid deadlock with
system suspend.  Do not allocate rx urb's constantly -
allocate once upon init, free rx urb upon exit.

Bug 929408, 952748, 957354

Change-Id: I4ea050fc881528cf44d2039d42891e21c9df8c4e
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
(cherry picked from commit 8bd7322127ccf6727d949f4bc1b2a4eac4b6814e)
Reviewed-on: http://git-master/r/95166
Reviewed-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Conflicts:
	drivers/net/usb/raw_ip_net.c
ARM: vfp: Prevent process migration

System crashes if there is process migration during vfp_init() call.

During vfp_init(), if a process which called vfp_enable() is migrated just
after the call, then the process executing the rest of code will access
a VFP unit which is not ENABLED and also smp_call_function() will not work
as it is expected.

This patch prevents process migration during vfp_init().

Bug 968524
Bug 961609
Bug 957974
Bug 958581
Bug 959838
Bug 946739

Change-Id: I18c0ff3af490578afd5add7a1d64cab8c8ebf487
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/98029
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
video: tegra: dsi: Add DSI register dump in debugfs.

Bug 951349

Change-Id: I79fb2e49fa38b83af78323b5f5cf6dbca8fd83c2
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/98512
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
video: tegra: host: Reset 3D after power on

Sometimes 3D unit comes up with incorrect scissor configuration.
Earlier patch added the scissor registers to the context save list,
but that did not solve the problem. Remove the extra registers, and
reset 3D after powering it up.

Bug 939307

Change-Id: Id795f2d99ec3c6b907da2785b1816ce753af7a3f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/87654
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Graziano Misuraca <gmisuraca@nvidia.com>
Tested-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>