hdl/modules/wb_un_cross/wbgen/*: update wbgen files

This update includes support for the new Windowing
algorithm
hdl/modules/wb_un_cross/*: add external generated clock input

Now, we have the possibility to get an external
generated switching clock and just delaying it by a
wishbone controllable register
hdl/modules/sw_windowing/*: add new Windowing module

This effectively applies a Window in the input signal
in order to reduce the switching noise in the FOFB rate
hdl/modules/Manifest.py: update Manifest file
hdl/modules/wb_position_calc/*: add Windowing module

Add Windowing module and debug signals
hdl/modules/dsp_cores_pkg.vhd: update components definitions
Merge branch 'windowing-integration' into pos_calc_wishbonized