latency: fixed bugs in test running and grapher
x300: Fixed typo in io_impl
x300: Cleaned up DAC ctrl and clock init logic

- DAC: Squashed configuration into 2 main operations: reset and reset_and_resync
- DAC: Put in sleep mode during configuration
- DAC: Synchronize only if streaming to more than one DAC
- DAC: Use falling edge sync mode
- DAC: Fixed power up/down settings
- DAC: Frontend sync failure is fatal
- Clocks: Refactored clock source change logic
- Clocks: Cleaned up init and lock-check sequence
examples: Fixed multi-channel ops
debug_prints_tool: New tool to plot the output of DEBUG_TXRX-enabled
output.
debug_prints_tool: Minor cleanup
e300: docs: Remove mention of E300 to not confuse people.

Signed-off-by: Moritz Fischer <moritz@ettus.com>
Merge branch 'maint'

Conflicts:
	host/examples/txrx_loopback_to_file.cpp
ks: record channels to separate files, 'ignore-' options for recv loop, corrected max_late_count calculation
ks: abort fix
ks: wrong TX CPU format was being printed (was printing RX for TX)
math: Added a portable log2()
b200: Make the master clock rate auto-configurable

When no master_clock_rate is defined, the B200 driver will now
select a suitable clock rate automatically based on the selected
sampling rate.
The selected tick rate is a multiple of the LCM of tx and rx rates.

Auto-setting is done every time a streamer is generated or the sampling
rate is configured.
x300: Clarified FPGA compat error message
b200: serialized access to get_rx/tx_stream
Merge branch 'maint'

Conflicts:
	host/lib/usrp/b200/b200_impl.hpp
uhd: replaced the `images_error` with a generic utility error

- Deleted images.*, moved functionality to paths.*
- Applies for all devices that check FPGA or FW compat numbers
- Adds generic utility search tool
multi_usrp: Handle auto_tick_rate properly
docs: Added notes on auto_tick_rate (B200)
docs: updating e310 front/rear panel images with latest drawings