[FIX] Fix AXI openMAC C_S_AXI_MIN_SIZE configuration

This fix solves wrong address decoder configuration used in the ipif core
for sub memory maps.

Change-Id: I28ec99c95d073be1cf889b67b58304fbb68984b9
[TASK] Remove test port in axi_openmac IP-Core

Change-Id: Ief4afa8047cc312e04e82b3135c7505ef324097b
[TASK] Rework hardware cmake integration for dual processor systems

Rework hardware cmake work flow enabling dual processor designs.
- Introduce settings for PCP and HOST processor instance
- Adapt drivers and embedded CN demo
- Revise Xilinx eclipse project files

Change-Id: I3a449a1d9cbf1ae984eaaf7548c5d4730473f92b
[FEATURE] Add FPGA design files for MN on Zynq SoC

- Add XPS project files and SDK support files to generate bsp
- Add eclipse configuration files for Xilinx ARM architecture
- Add additional bootimage.bif and intermediate makefile to generate boot.bin

NOTE: Modified system.xml file is added as a part of SDK project files to
      enable building of application on PCP (Microblaze) which is
      not possible with the tool generated file due to bug in tools.

Change-Id: I27523e58ef8d608cefc0ef5bebbc150a11f12e0c
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FEATURE] Add cmake configuration files for target Xilinx ARM

Add toolchain and global definition file to add cmake support
for Xilinx ARM EABI toolchain.

Change-Id: I170178ce251c72a26c6462d05e6ae12d71dbd5c0
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Add cmake compilation support for Xilinx ZC702 board design

- Update cmake configuration for hardware compilation
  to include design files for Xilinx ZC702.
- Add configuration file to support compilation using Xilinx ARM toolchain.

Change-Id: I2ffe80500ac3907b0659aa57e0e49d14a7e8d3e1
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FEATURE] Add dual processor lib using shared memory for non-OS systems

This library is designed for system where the user layer and kernel layer
of openPOWERLINK run on different processors and shared memory is used as the
interface between the two processors.

The dual processor library requires the hardware to support two types
of memory: Common and dynamic memory.

The common memory can be used for exchanging status, errors, states, etc.
and is used for creating dynamic memory mapping table used to share the
address for dynamically allocated shared memories.

Dynamic memory can be allocated at run time by any one of the processor and
these addresses are made available to the other processor through the dynamic
memory mapping table.

The library also provides support for handling interrupts for such
systems.

Change-Id: Id1cc80ef36c3dbbf29983ba3f95439da4e260c94
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FEATURE] Add SD FAT16 file system access library

This library provides a file system support to allow an application
running on ARM core of Zynq accessing files (CDC) on a SD CARD.

NOTE: Please refer to readme.md for this library license information!

Change-Id: I5f854f66967bb11ec91ef5bb6dcc27dfc60f5e7f
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Add support for target Xilinx ARM in stack

- Modify targetsystem.h to include dependencies and compiler support
  for target Xilinx ARM
- Add stack support files for target Xilinx ARM
- Add options file for cmake to support target Xilinx ARM

Change-Id: Ie3cea6fbb3906212baf3a794bdb3269a64fe5850
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FEATURE] Add CAL support modules for dual processor library

Event and DLL modules use queues based on circular buffers
for communication. The error handler and PDO module use
dynamically shared memory for error counters and data exchange.

Change-Id: Ia866921db6656e5088a1d1152336ce7d64d389a7
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Add support for dual processor design for target Microblaze

- Add target specific lock module for dual processor design
- Update target-microblaze.c to add support routines for Microblaze
  on Xilinx Zynq SoC
- Update configure-microblaze.cmake for single processor CN design to
  distinguish between single and dual processor lock module

Change-Id: Iaa2602a2c1b9c17b6866fb8b424dea1fec97ef66
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FEATURE] Add MN stack libraries for shared memory interface

- Add cmake based project files to compile MN stack libraries using
  shared memory interface for a dual processor system
- Update options-microblaze.cmake to include compilation of MN
  dual processor driver library for Microblaze target
- Add compilation option for target ARM to compile MN stack library

Change-Id: I2af104aa39d7645e4ff2c7d876627a91acabf801
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Add generic cache handling macros

Add cache handling macros in circular buffer and PDO modules to support data
cache usage on Zynq.

Change-Id: I76ee879844e7d49eb8d1d7e50719d5518709737a
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FEATURE] Add daemon application for Microblaze target

Add driver daemon for Microblaze with stack MN library using shared memory
interface support.

Change-Id: I42cf7c8a7af11e3fcc4e50ec5aac5df908b6e669
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FEATURE] Add support to run embedded MN demo on target Zynq SoC

The demo MN application for target Zynq SoC uses dual processor stack library.

The application for Zynq SoC is modified to use configuration file (mnobd.cdc)
placed on the SD card along with binaries instead of compiling it with source.

Change-Id: I7a02e441c50240eae4cfcf49d8192c1a6e4739ae
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Add Zynq SoC platform documentation

- Add platform documentation for Zynq SoC
- Update build steps for demos, drivers, hardware and stack to compile it for
  target Xilinx ARM

Change-Id: I853d0fd2cfc486812178e92185c1bde2df081709
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Add benchmark support for Xilinx ARM as host

Change-Id: I69a6a5cac3bc9ece3d8709df229df4651ebb649e
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Add Zynq FSBL project configuration

The Zynq first stage bootloader (FSBL) uses BOOT.bin file placed
on a FAT32 SDCARD initializing host and pcp binaries in the DDR memory.

The bootloader code is part of Xilinx install directory and is
imported and built through cmake for openPOWERLINK demos on Zynq.

Change-Id: I30d7ebaf134e1608d704709c0667b82795d6a4ea
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Update local memory sections for Microblaze MN

Change-Id: I350c6cc2e35d2403a783613afe065f3f6873fd77
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Fix referenced bsp for eclipse project

Change-Id: I0a9222e0ce77d8d642b627b6c80c0c7b483a0941