libbladeRF: Added additional elaboration to SC16Q11 format
hdl: Added option to divide sample counter by two

The sample counter increments once per I and once per Q. However,
the host side will want timestamps that increment once per entire
sample.
hdl: Fixed timestamp readback.

Inserted an appropriate handshake to the time_tamer module for reading
back the current timestamp of either the TX or RX timestamp.
hdl: Fixed timing issue in time_tamer.vhd

Some bits of the timestamp values were reading out incorrectly.
Registered the output on the rising edge of the clock to address this.
hdl: Making some timestamp changes.
hdl: Adding TX NOW and RX metadata gating.

Adding a zero sample to the beginning of the burst tests so initial
power out from the LMS is minimized.

I tried adding a single sample to the DAC output but it didn't seem
to want to work appropriately, so there is around 700us worth of output
power after an initial boot of the board and loading of the FPGA.
hdl: Sending a few more samples when first enabled

Helps mitigate the high default output power from the LMS after
initialization of the device.  The observed time appears <200us.
libbladeRF: Removed SC16_Q12 reverse compat macro

This has been scheduled for removal since RC1 and RC2.
libbladeRF: Updated outdated comments

The situation has changed since thread-safety changes in 7b0cc24f.
libbladeRF: Workaround for deadlock condition

This is a workaround for issue (#324).

We appear to have a lock ordering issue with our stream->lock and the underlying
libusb event lock.  When a libusb event occurs, it acquires its event lock and
then our callback acquires a stream lock.  When we asynchronously submit a
transfer, we acquire the stream lock and then libusb acquires its event lock
under the hood. If a callback occurs while we're submitting a transfer on the
same stream, deadlock ensues, due to the above asymmetry in lock acquisition.

Ultimately, we'll need to review our locking scheme and libusb event handle to
address underlying design issues here, and potentially trim some fat.

For now, the lock is just dropped after all metadata has already been updated,
and reacquired after submission.
libbladeRF: Added API definition for FPGA counter mode enable bit
libbladeRF: Introduced timestamp metadata support for sync data i/f

API support for timestamp metadata has been introduced. This is made
available when using the newly introduced BLADERF_FORMAT_SC16_Q11_META
format value.

When using the synchronous interface, metadata is exchanged between the
caller and the API via the updated bladerf_metadata structure. Users of
the asynchronous interface must currently manually manage the metadata
headers as desired, as documented in libbladeRF.h.

When using the BLADERF_FORMAT_SC16_Q11_META format in conjunction with
the synchronous interface, it is possible to retrieve the timestamp for
received samples and an indication of overrun.  An RX operation may also
be scheduled for at a specific timestamp value the future.  Similarly,
bursts of samples can be scheduled to be transmitted at a specific
timestamp value, or at the first available timestamp ("now").
libbladeRF: Added more complete examples for the synchronous interface

The existing bladerf_sync_rx() snippet in the libbladeRF API docs has
been replaced by a more complete snippet in libbladeRF/doc/examples.

From now on, major snippets and examples to be included in
Doxygen-generated documentation shall now be placed in the
libbladeRF/doc/examples directory, and must be buildable and testable.

The Doxygen "snippet" command to shall be used to include the relevant
code from the example program.
libbladeRF: Made enumeration value references Doxygen links