drm/tegra: output: Make ->setup_clock() optional

In order to transition output drivers to using the struct tegra_output
as a helper rather than midlayer, make this callback optional. Instead
drivers should implement the equivalent as part of ->mode_fixup(). For
the conversion to atomic modesetting a new callback ->atomic_check()
should be implemented that updates the display controller's state with
the corresponding parent clock, rate and shift clock divider.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: Add tegra_dc_setup_clock() helper

This is a small helper that performs the basic steps required by all
output drivers to prepare the display controller for use with a given
encoder.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: hdmi: demidlayer
drm/tegra: sor: demidlayer
Revert "Revert "drm/dsi: Request ACK for DCS commands""

This reverts commit 7fad41c654641c47d868d5817aa59e31768effaa.
iommu/tegra: Correctly keep track of usage count

The address space usage count needs to be incremented every time a
device is attached to a domain, otherwise the device detachment code
will prematurely free the address space.

Signed-off-by: Thierry Reding <treding@nvidia.com>
iommu/tegra: Properly detach devices from domains

of_parse_phandle_with_args() returns 0 on success, so use the proper
check while iterating over the phandles and arguments.

Signed-off-by: Thierry Reding <treding@nvidia.com>
iommu/tegra: Do not leak device tree nodes

The of_parse_phandle_*() family of iterators returns a device tree node
with increased reference count and requires callers to dereference the
nodes using of_node_put() when they are no longer needed.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dsi: Demidlayer

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: hdmi: demidlayer
dsi demidlayer
drm/tegra: sor: demidlayer
WIP: drm/tegra: Atomic conversion, phase 1

TODO:
- Find out why DSI breaks if DC_CMD_DISPLAY_POWER_CONTROL is cleared at
  ->disable() time.

  Currently the driver still clears the bits in this register, but that
  has the side-effect of disabling the display controller, resulting in
  VBLANK interrupts ceasing and therefore the atomic helpers not being
  able to clean up properly.

Signed-off-by: Thierry Reding <treding@nvidia.com>
WIP: drm/tegra: Atomic conversion, phase 2

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: Atomic conversion, phase 3, step 1

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: Atomic conversion, phase 3, step 2

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: Atomic conversion, phase 3, step 3

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/atomic: Add drm_atomic_plane_get_crtc_state()

This function is useful to obtain the state of the CRTC that a plane is
being attached to.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: Track active planes in CRTC state

Wrap struct drm_crtc_state in a driver-specific structure and add the
planes field which keeps track of which planes are updated or disabled
during a modeset. This allows atomic updates of the the display engine
at ->atomic_flush() time.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: Track tiling and format in plane state

Signed-off-by: Thierry Reding <treding@nvidia.com>