Reset CNTVOFF_EL2 register before exit into EL1 on warm boot

This patch resets the value of CNTVOFF_EL2 before exit to EL1 on
warm boot. This needs to be done if only the Trusted Firmware exits
to EL1 instead of EL2, otherwise the hypervisor would be responsible
for this.

Fixes ARM-software/tf-issues#240

Change-Id: I79d54831356cf3215bcf1f251c373bd8f89db0e0
Juno: Use TZC-400 driver calls

This patch replaces direct accesses to the TZC-400 registers by the
appropiate calls to the generic driver available in the Trusted
Firmware in order to initialize the TrustZone Controller.

Functions related to the initialization of the secure memory,
like the TZC-400 configuration, have been moved to a new file
'plat_security.c'. This reorganization makes easier to set up
the secure memory from any BL stage.

TZC-400 initialization has been moved from BL1 to BL2 because BL1
does not access the non-secure memory. It is BL2's responsibility
to enable and configure the TZC-400 before loading the next BL
images.

In Juno, BL3-0 initializes some of the platform peripherals, like
the DDR controller. Thus, BL3-0 must be loaded before configuring
the TrustZone Controller. As a consequence, the IO layer
initialization has been moved to early platform initialization.

Fixes ARM-software/tf-issues#234

Change-Id: I83dde778f937ac8d2996f7377e871a2e77d9490e
Merge pull request #206 from soby-mathew/sm/reset_cntvoff

Reset CNTVOFF_EL2 register before exit into EL1 on warm boot
Juno: Reserve some DDR-DRAM for secure use

This patch configures the TrustZone Controller in Juno to split
the 2GB DDR-DRAM memory at 0x80000000 into Secure and Non-Secure
regions:

- Secure DDR-DRAM: top 16 MB, except for the last 2 MB which are
  used by the SCP for DDR retraining
- Non-Secure DDR-DRAM: remaining DRAM starting at base address

Build option PLAT_TSP_LOCATION selects the location of the secure
payload (BL3-2):

- 'tsram' : Trusted SRAM (default option)
- 'dram'  : Secure region in the DDR-DRAM (set by the TrustZone
            controller)

The MMU memory map has been updated to give BL2 permission to load
BL3-2 into the DDR-DRAM secure region.

Fixes ARM-software/tf-issues#233

Change-Id: I6843fc32ef90aadd3ea6ac4c7f314f8ecbd5d07b
Juno: Support entry into a standby state

This patch adds support on the Juno platform for entering a wfi in
response to a PSCI CPU_SUSPEND call where the state type is a
standby state.

Change-Id: I0a102dee1f8d2ad936c63ad1d1d3ad001a4a4768
FVP: keep shared data in Trusted SRAM

This patch deprecates the build option to relocate the shared data
into Trusted DRAM in FVP. After this change, shared data is always
located at the base of Trusted SRAM. This reduces the complexity
of the memory map and the number of combinations in the build
options.

Fixes ARM-software/tf-issues#257

Change-Id: I68426472567b9d8c6d22d8884cb816f6b61bcbd3
Merge pull request #215 from jcastillo-arm/jc/juno_mem_6

Jc/juno mem 6
Merge pull request #216 from vikramkanigiri/vk/juno_standby_support

Juno: Support entry into a standby state
Merge pull request #217 from jcastillo-arm/jc/tf-issues/257

FVP: keep shared data in Trusted SRAM
Add support for level specific cache maintenance operations

This patch adds level specific cache maintenance functions
to cache_helpers.S. The new functions 'dcsw_op_levelx',
where '1 <= x <= 3', allow to perform cache maintenance by
set/way for that particular level of cache.  With this patch,
functions to support cache maintenance upto level 3 have
been implemented since it is the highest cache level for
most ARM SoCs.

These functions are now utilized in CPU specific power down
sequences to implement them as mandated by processor specific
technical reference manual.

Change-Id: Icd90ce6b51cff5a12863bcda01b93601417fd45c
Apply errata workarounds only when major/minor revisions match.

Prior to this patch, the errata workarounds were applied for any version
of the CPU in the release build and in the debug build an assert
failure resulted when the revision did not match. This patch applies
errata workarounds in the Cortex-A57 reset handler only if the 'variant'
and 'revision' fields read from the MIDR_EL1 match. In the debug build,
a warning message is printed for each errata workaround which is not
applied.

The patch modifies the register usage in 'reset_handler` so
as to adhere to ARM procedure calling standards.

Fixes ARM-software/tf-issues#242

Change-Id: I51b1f876474599db885afa03346e38a476f84c29
Optimize barrier usage during Cortex-A57 power down

This the patch replaces the DSB SY with DSB ISH
after disabling L2 prefetches during the Cortex-A57
power down sequence.

Change-Id: I048d12d830c1b974b161224eff079fb9f8ecf52d
Optimize Cortex-A57 cluster power down sequence on Juno

This patch optimizes the Cortex-A57 cluster power down sequence by not
flushing the Level1 data cache. The L1 data cache and the L2 unified
cache are inclusive. A flush of the L2 by set/way flushes any dirty
lines from the L1 as well. This is a known safe deviation from the
Cortex-A57 TRM defined power down sequence. This optimization can be
enabled by the platform through the 'SKIP_A57_L1_FLUSH_PWR_DWN' build
flag. Each Cortex-A57 based platform must make its own decision on
whether to use the optimization.

This patch also renames the cpu-errata-workarounds.md to
cpu-specific-build-macros.md as this facilitates documentation
of both CPU Specific errata and CPU Specific Optimization
build macros.

Change-Id: I299b9fe79e9a7e08e8a0dffb7d345f9a00a71480
Merge pull request #218 from soby-mathew/sm/add_cpu_ops_warning

Add level specific cache operations and changes to errata workaround mechanism
Improvements to ARM GIC driver

This patch introduces several improvements to the ARM GIC driver:

* In function gicd_set_itargetsr(), target CPU is specified using
  the same bit mask detailed in the GICD_ITARGETSRn register instead
  of the CPU linear ID, removing the dependency between bit position
  and linear ID in the platform porting. The current CPU bit mask
  may be obtained by reading GICD_ITARGETSR0.

* PPIs and SGIs are initialized in arm_gic_pcpu_distif_setup().
  SPIs are initialized in arm_gic_distif_setup().

* By default, non secure interrupts are assigned the maximum
  priority allowed to a non secure interrupt (defined by
  GIC_HIGHEST_NS_PRIORITY).

* GICR base address is allowed to be NULL for GICv1 and GICv2.

Change-Id: Ie2837fe860d43b2282e582dfdb13c39c6186f232
Juno: Use the generic ARM GIC driver

This patch replaces the usage of the GIC private driver in Juno with
the generic ARM GIC driver. The private driver is no longer necessary
and has been removed from the Juno port.

Fixes ARM-software/tf-issues#253

Change-Id: I6aaabc252e5e6fb5fcf44ab6d0febd9b38791056
Merge pull request #219 from jcastillo-arm/jc/tf-issues/253

Improvements to ARM GIC driver
Juno: Use the generic ARM GIC driver
Use the BL3-1 runtime console as the crash console.

This patch reassigns the crash console on Juno and FVP to use the runtime
BL3-1 console. The crash console is changed to SoC UART0 (UART2) from the
previous FPGA UART0 (UART0) on Juno. In FVP, it is changed from UART0 to
UART1.

Fixes ARM-software/tf-issues#256

Change-Id: I7df54f86ca00ec2652c27261dd66a94c12610816
Precede a 'sev' with a 'dsb' in bakery lock code

This patch fixes a bug in the bakery lock implementation where a data
synchronisation barrier instruction is not issued before sending an event as
mandated by the ARMv8 ARM. This can cause a event to be signalled before the
related memory accesses have completed resulting in erroneous execution.

Fixes ARM-software/tf-issues#272

Change-Id: I5ce02bf70afb001d967b9fa4c3f77442931d5349
Merge pull request #221 from achingupta/ag/tf-issues#272

Precede a 'sev' with a 'dsb' in bakery lock code