base: fix missing barriers in lock back-end

:Lock barriers on ARM:

The compiler memory-barrier prevents the compiler from changing the
program order of memory accesses in such a way that accesses to the
guarded resource get outside the guarded stage. However, the
architectural memory model allows not only that memory accesses take
local effect in another order as their program order but also that
different observers (components that can access memory like data-busses,
TLBs and branch predictors) observe these effects each in another order.
Thus, a correct program order isn't sufficient for a correct observation
order. An additional architectural memory-barrier is needed to achieve
this.

:Lock barriers on X86:

The compiler memory-barrier prevents the compiler from changing the
program order of memory accesses in such a way that accesses to the
guarded resource get outside the guarded stage. This is sufficient as
the architecture ensures to not reorder writes with older reads, writes
to memory with other writes (except in cases that are not relevant for
our locks), or read/write instructions with I/O instructions, locked
instructions, and serializing instructions.

fix #692