Fixes #128
split out count for errors/warnings
color code errors and warnings
follow sbt error/warning format
Throw exception if any of Chisel Tester vectors fail. Example functional test in WhenSuite, using cpp backend.
Fixed ROM generation. Issue was Vec and ROM were both generating verilog. In addition, the ROM generated verilog was incorrect. Test added to test suite.
Merge branch 'master' of https://github.com/ucb-bar/chisel
Clean up Verilog literal generation
Clean up Op code
Fix handling of ? literals in verilog
Added flags to eliminate $random() during synthesis for ROM generation
Merge branch 'master' of https://github.com/ucb-bar/chisel

Conflicts:
	src/test/resources/DelaySuite_ROMModule_1.v
Fixed ROM test with cleaned-up Verilog generation
fix #73
Merge branch 'master' of https://github.com/ucb-bar/chisel
warn for assign to own input
merge
Remove unused Lit field
Remove ListLookup from backend; implement with Muxes
Revert "warn for assign to own input"

Unfortunately, this good idea breaks several built-in tests and real
designs.  I tried for an hour to figure out why, but couldn't.