sioplus iosched: change fifo batching logic to a sane one

Before this commit, there was always one more request
batched than set via the fifo_batch sysfs variable.
E.g., a setting of 1 would suggest that 1 request would
be handled as a batch, but instead 2 requests were batched.
This is not very logical.

Now, the pre-set setting of fifo_batch = 1 ensures that each
request is handled on its own, which is what we want for
flash memory devices.
sioplus iosched: change write starvation logic to a sane one

Before this commit, there was always one more dispatched
read request necessary than set via the writes_starved
sysfs variable. This is not logical. Fix this.
sioplus iosched: fix wrong batch counting logic

Before this commit, the batch counter was increased
with any dispatched request. This does not make sense:
Every time an expired request was picked due to the
batch counter reaching its barrier, the batch counter
was increased, effectively reducing (=crippling)the
following non-expired batch. Fix this.
sioplus iosched: update description text
sioplus iosched: tweaks (adjusting the iosched to recent changes)

Conflicts:
	block/sioplus-iosched.c
ARM: mm: Optimise the v7 Dcache flush all routine.

The current algorithm flushes using the SET and WAY, where it iterates over
a given SET in all the WAYS and to the next SET. Change this so that every
successive flush address will go to in to the alternate EMIF(1/2), there by
utilising the full bandwidth. Also iterating all the SETS of a given WAY,
and then switching to the next way can reduce the possibility of frequent
change in the row bits during successive transactions of the DDR memory.
This will help in reducing the ROW open/close time.

Signed-off-by: Marquette Anderson <m-anderson13@ti.com>
ARM: mm: Avoid the use of r8 register in cache flush all/level apis.

Currently cache_flush_by_level API is called from __v7_setup.
At this point, r8 contains the initial TTBR1 base address.
But r8 is not saved/restored in the API, resulting in corrupting
it. So when the corrupted r8 is used further during the
boot sequence, causes weird issues.

The issue becomes evident when the ARM workaround to use
"TTBR1 instead of reserved ASID during the context switch"
is applied.

Fixing this by optimising the code to avoid using r8.

Also there was a issue with optimise patch corrupting r3.
This has no functional impact, but resulted in unnessecary
cmp instructions.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
ARM: 6995/2: mm: remove unnecessary cache flush on v6 copypage

Originally introduced to maintain coherency between icache and dcache
in v6 nonaliasing mode. This is now handled by __sync_icache_dcache since
c0177800, therefore unnecessary in this function.

Signed-off-by: Heechul Yun <heechul@illinois.edu>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>