verilog: Support for Verilog 2001 port declaration

Starting from version 2001, the Verilog standard allows module
declaration in the following format:

module module_name (
    input wire a,
    output reg b
);

This patch adds a check to confirm if the name of the port is not a
keyword, guaranteeing that the port net type is not added as a port by
mistake.
verilog: Use macro to get vString length
verilog: Add scope information extraction

Add tokenInfo structure and required helper functions to implement a
push/pop stack containing the current context of the tags being found.
verilog: Add basic support for SystemVerilog

Only includes extra support for "logic" register data type and "class".