MC: Diagnose an unexpected token in COFF .section instead of asserting

This can easily arise when trying to assemble and ELF style .section
directive for a COFF object file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215373 91177308-0d34-0410-b5e6-96231b3b80d8
Add missing test for r215031

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215374 91177308-0d34-0410-b5e6-96231b3b80d8
Correct a missing RUN line in the ARM codegen test for fneg ops. We should also explicitly specify +/-neonfp.

The bug was introduced at r99570 when use of "-arm-use-neon-fp" was removed.

Differential Revision: http://reviews.llvm.org/D4846



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215377 91177308-0d34-0410-b5e6-96231b3b80d8
Fix using -plugin-opt=apiflie when also using -plugin-opt=emit-llvm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215378 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: try harder to detect non-IT eligible instructions

For many Thumb-1 register register instructions, setting the CPSR is not
permitted inside an IT block.  We would not correctly flag those instructions.
The previous change to identify this scenario was insufficient as it did not
actually catch all the instances.  The current list is formed by manual
inspection of the ARMv6M ARM.

The change to the Thumb2 IT block test is due to the fact that the new more
stringent checking of the MIs results in the If Conversion pass being prevented
from executing (since not all the instructions in the BB are predicable).  This
results in code gen changes.

Thanks to Tim Northover for pointing out that the previous patch was
insufficient and hinting that the use of the v6M ARM would be much easier to use
than the v7 or v8!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215382 91177308-0d34-0410-b5e6-96231b3b80d8
Debug info: Refactor DebugLocEntry's Merge function to make
buildLocationLists easier to read.

The previous implementation conflated the merging of individual pieces
and the merging of entire DebugLocEntries.

By splitting this functionality into two separate functions the intention
of the code should be clearer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215383 91177308-0d34-0410-b5e6-96231b3b80d8
Debug Info: Move the sorting and uniqueing of pieces from emitLocPieces()
into buildLocationList(). By keeping the list of Values sorted,
DebugLocEntry::Merge can also merge multi-piece entries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215384 91177308-0d34-0410-b5e6-96231b3b80d8
Debug info: Further simplify the implementation of buildLocationList by
getting rid of the redundant DIVariable in the OpenRanges pair.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215385 91177308-0d34-0410-b5e6-96231b3b80d8
Debug info: Modify DebugLocEntry::addValue to take multiple values so it
only has to sort/unique values once per batch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215386 91177308-0d34-0410-b5e6-96231b3b80d8
Debug info: Remove an obsolete constructor from DebugLocEntry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215387 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64] Fix registerAllocator assigns same register for base and wback in
pre/post-index load and store.

Patch by Steven Wu <stevenwu@apple.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215390 91177308-0d34-0410-b5e6-96231b3b80d8
Add isRegSequence property.

This patch adds a new property: isRegSequence and the related target hooks: 
TargetIntrInfo::getRegSequenceInputs and 
TargetInstrInfo::getRegSequenceLikeInputs to specify that a target specific
instruction is a (kind of) REG_SEQUENCE.

<rdar://problem/12702965>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215394 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Fix broken test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215395 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Clear lds bit on MUBUF instructions used for private stores

This bit was left uninitialized, which was causing some random failures
of piglit tests.

NOTE: This is a candidate for the 3.5 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215396 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Add check for low 32 bits of encoding to mubuf tests

There are no variable values like registers encoded in the low 32 bits of MUBUF
instructions, so it is relatively easy to check these bits, and it will
help prevent us from introducing encoding bugs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215397 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Add an _OFFEN variant MUBUF_STORE_* and use it for scratch writes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215398 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variant

This saves us from having to copy a 64-bit 0 value into VGPRs for
BUFFER_* instruction which only have a 12-bit immediate offset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215399 91177308-0d34-0410-b5e6-96231b3b80d8
InstCombine: Combine (add (and %a, %b) (or %a, %b)) to (add %a, %b)

What follows bellow is a correctness proof of the transform using CVC3.

$ < t.cvc
A, B : BITVECTOR(32);

QUERY BVPLUS(32, A & B, A | B) = BVPLUS(32, A, B);

$ cvc3 < t.cvc
Valid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215400 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: Tidy up a few comments.

Have the comments match the actual parameter names. Found via clang-tidy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215401 91177308-0d34-0410-b5e6-96231b3b80d8
Add missing closing namespace comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215402 91177308-0d34-0410-b5e6-96231b3b80d8