Fix for pretty-printing of Modules with no internal signals

In cases where VHDL syntax requires semicolons *after* lines, not *between* them, don't emit a semicolon for empty lists.

This fixes a VHDL syntax error in the pretty-printed output of e.g.

```haskell
Module "Empty" [] [] [] [InstDecl "work.foo" "foo" [] [] []]
```

which without this patch is pretty-printed as

```vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Empty is
  port();
end entity Empty;
architecture str of Empty is
  ;
begin
  foo : entity work.foo
  port map ();
end architecture str;
```

The stray `;` at the beginning of the `architecture` block is a syntax error in VHDL.