first commit:CV
dev_rev1: changed permissions on build.sh:CV
added board settings to system.bdf:CV
edited system.bdf (AxiFIFO) with board mac:CV
changed permissions on build.sh(AxiFIFO):CV
added new folder /modules to /dev branch:CV
changed folder name AxiFIFO and build.sh for zed:CV
removed modules/AxiFIFO:CV
dev_revison2: added new source files for zed board to root and rebuilt with gradle, synthesis still failing:axi port error port is driven by sourceless connector:CV
dev_revision3: added new generated fifo core for zed synthesis test:CV
dev_revision3:edited system.bdf for new zed core:CV
dev_revision3:changed config srcs for zed:CV
changed dir name for a second try:CV
rm on AxiFIFO_zed
rm temp in Axi_zed
clean sources for zed:CV
rm old sources
changed README file:CV
Merge pull request #18 from mweberUKL/development

Checksum and multiple modules/axi ports fix
removed files which are under Xilinx Copyright
added a script which copies these files automatically after adjusting the Paths inside the script