[CORE] Allow a different IRQ chip for extended IRQ mapping.

Some drivers will need a different IRQ chip to manage the extended IRQS. For
example, GPIO drivers, as the i.MX one, may define PIN specific extended IRQs.
[DRIVERS] Many corrections on the i.MX GPIO driver.

- Setting IRQ type retrived the wrong GPIO PIN number.
- The extended IRQ handling was not correctly done, calling the IRQ handler
instead of the associated IRQ actions.
- The HW IRQ chip was set on the GPIO IRQ one, leading to an IRQ never set as
processed to the GIC controller.
- The IRQ generic chip is now set for the extended IRQ, and the GIC chip is
left for the HW one.
- The extended IRQ now mask, unmask, and ack the GPIO controller IRQ, through
the GPIO IRQ chip.
[DRIVERS] Inverting the IRQ type set and registering calls.
[ARM] Correcting i.MX clock controller interrupt numbers.
[DRIVERS] Improving i.MX GPIO driver.
[CORE] Extended IRQs improvments for xvisor-next done.

- The extended IRQs are now always enabled.
- Macros and structures have been renamed to all have a "host_extirq" part in
  common.
- The "vmm_host_extirqs" structure have been renamed "vmm_host_extirq_group".
- A bitmap is used for extended IRQ allocation.
- Error management have been improved.
- A rework to allow using Linux "irq_domain" have been done, but you have to
  use "vmm_host_extirq_to_hwirq" to convert an global IRQ to the domain IRQ.

Moreover, group allocation is dynamic, using a "dlist".
[COMMANDS] Adding extended IRQ command.

A new command, "host extirq stats" have been added to dump extended IRQs.
For now, it is more to debug extended IRQs, but it should evolve quickly to a
better command interface.
[DRIVERS] Updating i.MX GPIO driver for extended IRQs.
[DRIVERS] Adding SDHCI tuning command support.
[DRIVERS] Removing MMC/SDHCI unused fields.
[ALL] Corecting various warnings, visible with level 1 optimization.
n[DRIVERS] i.MX SPI driver completion modified.

i.MX SPI IRQ are disabled too early, and led to an infinite wait on the
"wait_for_completion" in the "spi_imx_transfer" function.
A temporary hack is to wait with a timeout, reenabling the IRQ on a timeout.
[ARM] Setting read-only section MMU entries as read only.

The linker script sections have been reorganized and split to set different
places for read-only and read-write sections, and the MMU L2 entries are now
set as priviledged read-write access or priviledged read-only access.
".init.data" have been renamed ".initdata" to avoid initialization data
to fall in the linker script ".init" section.
Uninitialized data have been set into the '.bss' sections.
[ARM] Once written, set the IRQ vector as a read-only page.

To avoid IRQ vector corruption, set the IRQ vector page as read-only.
This mean that the virtual page must be first mapped with read-write privileged
access, and after being written, set to read-only.
[DRIVERS] Correcting i.MX SDHCI device tree property function calls.

The property length parameter must be set, as the NULL pointer is not checked.
[DRIVERS] i.MX serial driver TX FIFO value corrected.

The TX FIFO trigger level must be set with a correct value, even without using
TX interruptions.
[DRIVERS] Use the SDHCI board controller specific clock setting function.

The SDHCI driver clock setting function should only use the board controller
specific one if it is set, as the clock rate can be specific (as it is on the
i.MX6 board).
[DRIVERS] Spin locking SDHCI driver functions.
[DRIVERS] TEMPORARY: Disable DMA usage for SDHCI drivers.

As the i.MX6 DMA channels are not supported yet, disable their usage for now
in the SDHCI driver.
[ARM] Compiling with -O1 optimization level.