Get actual pulse lines in working. Only connected lines 5-8 for now.

Using the top section of the HSMC A header port.  From the Altera dev. board user guide Table 2-37 using CMOS ports 40-45 as a 2.5 CMOS signal.  Tested and seems to work mostly okay.  It almost appears there is some caching on the PCI memory write/reads though.
Add copyright lines to my VHDL modules.
Add a little user function to count pulses from the 16 lines.