msm_fb: display: fix the underrun issue when playing interlaced videos

Interlaced videos require higher mdp clk rate and the current code
sets mdp clk to max and return. However mdp clk calculation may still
give a result higher than max mdp clk, for this case the result is
kept and used later to enable blt mode to avoid underrun.

Change-Id: I185d0d15e5b79e94561e790e41713cdb405f8bf4
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
msm_fb: Keep LCDC timing generator enabled during boot up

Keep the LCDC timing generator enabled during boot up on
MDP 3.03 targets if continuous splash screen feature is enabled.

Change-Id: I64276550f28e1f316c420f9cb158f7b8e938b8ea
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>

Conflicts:

	drivers/video/msm/mdp_hw_init.c
msm_fb: display: add mdp clk rate calculation for low vbp

For the panels that have low v_back_porch, if h/w FIR scaling is used,
during vbp time, mdp clk should be fast enough to output a line from 4
input lines. MDP rate equation for very small scaling, e.g. 1 or 2
pixels' upscaling or downscaling cannot cover this case, where
underruns are seen on those panels.

Change-Id: I4f35f98c2c1bc4ef04dfee193427bd3ff674945d
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
msm_fb: display: Fix blend configuration for MDP4.1

MDP4.1 blend operation registers are not double buffered and
take effect as soon as they are configured. Configuring these
registers at any place other than between dma and vsync produce
flickers as new blend values would get applied to previous
mixer configurations. Configure blend operation registers just
after dma is over, before vsync.

Change-Id: I377c11222f7a0cd77e98e90edec6e2e1dc0c17ca
Signed-off-by: Pradeep Jilagam <pjilagam@codeaurora.org>

Conflicts:

	drivers/video/msm/mdp4_overlay.c
cpufreq: fix error

Change-Id: Iab37b00a7c27f6af6e193956b073124a8c5d3bab