arm: Don't speculatively access most miscregisters.

Speculative exeuction can cause panics in detailed execution mode that
shouldn't happen.
mem: have WriteInvalidate obsolete MSHRs

Since WriteInvalidate directly writes into the cache, it can
create tricky timing interleavings with reads and writes to the
same cache line that haven't yet completed.  This patch ensures
that these requests, when completed, don't overwrite the newer
data from the WriteInvalidate.
mem: don't inhibit WriteInv's or defer snoops on their MSHRs

WriteInvalidate semantics depend on the unconditional writeback
or they won't complete.  Also, there's no point in deferring snoops
on their MSHRs, as they don't get new data at the end of their life
cycle the way other transactions do.

Add comment in the cache about a minor inefficiency re: WriteInvalidate.
cpu: Fix barrier push to store buffer when full bug in Minor

This patch fixes a bug where a completing load or store which is also a
barrier can push a barrier into the store buffer without first checking
that there is a free slot.

The bug was not fatal but would print a warning that the store buffer
was full when inserting.
cpu: Add support to checker for CACHE_BLOCK_ZERO commands.

The checker didn't know how to properly validate these new commands.
arm: Mark some miscregs (timer counter) registers at unverifiable.

The checker can't verify timer registers, so it should just grab the version
from the executing CPU, otherwise it could get a larger value and diverge
execution.
arm: fix bare-metal memory setup.

The bare-metal configuration option still configured memory with the old scheme
that no-longer works. This change unifies the code so there aren't any differences.
arm: Fix multi-system AArch64 boot w/caches.

Automatically extract cpu release address from DTB file.
Check SCTLR_EL1 to verify all caches are enabled.
arm, mem: Fix drain bug and provide drain prints for more components.
cpu: Add drain check functionality to IEW

IEW did not check the instQueue and memDepUnit to ensure
they were drained.  This caused issues when drainSanityCheck()
did check those structures after asserting IEW was drained.
cpu: Add writeback modeling for drain functionality

It is possible for the O3 CPU to consider itself drained and
later have a squashed instruction perform a writeback.  This
patch re-adds tracking of in-flight instructions to prevent
falsely signaling a drained event.
arm, tests: Update config files to more recent kernels and create 64-bit regressions.

This changes the default ARM system to a Versatile Express-like system that supports
2GB of memory and PCI devices and updates the default kernels/file-systems for
AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some
platforms that are no longer supported have been pruned from the configuration files.

In addition a set of 64-bit ARM regressions have been added to the regression system.
tests: Update regressions for the new kernels and various preceeding fixes.
automated merge