Fixed byte swap in C167 bus and fixed ports that drive DONE and DLL LEDs

added the signal vdif_DLL at pin M31
Fixed byte swap in C167 bus and fixed ports that drive DONE and DLL LEDs

reversed the order of the 8-bit bus from the C167 to take care fo the byte flip
added a port called DLL ta take care of driving the DLL LED on the PIC
Fixed the byte swap in C167 bus and fixed ports that drive DONE and DLL LEDs

reversed the order of the 8-bit bus from the C167 to take care of byte flip
add port DLL
assign DONE and DLL to '1'
Fixed byte swap in C167 bus and fixed ports that drive DONE and DLL LEDs

reversed the order of the 8-bit bus from the C167 to take care of the byte flip
added port DLL
Fixed byte swap in C167 bus and fixed ports that drive DONE and DLL LEDs

reversed the order of the 8-bit bus from the C167 to take care of byte flip
add port DLL
System as used for initial PICA bench test

added the signal vdif_AUXTIME_p/n
System as used for initial PICA bench test

added the port AUXTIME_p/n
System as used for initial PICA bench test

added AUXTIME
added PPS_PIC_p/n signals
drive DAC_CLK with adc_clk
drive PPS_PIC_sig with test_ctr(0) for a test source on backplane connector
drive DAC bits with test_ctr(7 downto 4)
change inputs to test point muxes to include all differential inputs in motherboard connector
drive test point muxes from C167_reg1 and C167_reg2
drive all ROUTB test points.  ROUTB(3) gets copy of 125 MHz clock for in-system test
drive test_ctr_fifo with 125 MHz system clock as an alternate test of 125 MHz.
System as used for initial PICA bench test

add AUXTIME
All registers required by the C167 interface have been added and tested

added lib treg8 for registers associated with C167 interface
all registers required by C167 microprocessor interface added and tested

The C167 interface was changed to address-based rather than select-line based
All registers required by C167 microprocessor interface added and tested

also commented our a fair amount of code related to VLBA design.  It can likely be deleted at a later date.
Made input clock to MMCM selectable via C167 interface register 0 bit 0.
C167 interface changed to address-based rather than select-line based.
ll registers required by C167 microprocessor added and tested

This is the initial commit of a register component required by the C167 code
all registers required cy C167 interface added and tested

Initial commit of mux64 which has been used for a while by opb_vdif_interface.vhd
data interface module added and tested

added files needed by the data_interface module
data interface module added and tested

Initial commit
Contains sub-modules sum_data_chk.vhd, test_data_gen.vhd and out_data_sel.vhd
Simply ties these modules together and to the opb_vdif_interface.vhd
data_interface module added and tested

Added signals required for interfacing to and testing data_interface
data_interface module added and tested

Initial commit
selects between normal data and one of two test signals:PRG and up-counter
data_interface module added and tested

Contains the logic to test input data against PRG
Contains the logic to acquire statistics of input data signals
data_interface module added and tested

Initial commit
Generates the internal PRN and counter test signals
Contains sub-module test_prg.vhd