testsuite/test-code-or1k/configure{,.ac}: force CCASFLAGS=-g

2013-04-03  Peter Gavin  <pgavin@gmail.com>

	* configure, configure.ac: force CCASFLAGS=-g so the value from
	the environment doesn't get used
add some new SPRs from version 1.0-rev0 of the architecture manual

* ChangeLog:

2013-04-03  Peter Gavin  <pgavin@gmail.com>

        * cpu/or1k/spr-defs.h, cpu/or1k/spr-dump.c: add some new SPRs from
        newest version of architecture manual (v1.0-rev0)

* testsuite/test-code-or1k/ChangeLog:

2013-04-03  Peter Gavin  <pgavin@gmail.com>

        * support/spr-defs.h: add some new SPRs from newest version of
        architecture manual (v1.0-rev0)
cpu-config.c (cpu_cfgr): improve checking of config register setting

2013-04-03  Peter Gavin  <pgavin@gmail.com>

        * cpu-config.c: (cpu_cfgr) improve checks on configuration, ensure
        that OB32S is always set, and that unsupported features are
        unset. Print a warning whenever configuration is changed from
        whatever was specified in the file
add support for AECR/AESR, use 32x32 to 64-bit multiply

* ChangeLog:

2013-04-04  Peter Gavin  <pgavin@gmail.com>

	* cpu/or32/insnset.c: change implementations of l_add, l_addc,
	l_sub, l_mul, l_mulu, l_div, and l_divu to match current
	architecture manual revision (1.0-rev0):
	- add AECR/AESR support.  Only used when AECSRP bit in CPUCFGR is
	set, otherwise exception is raised when OVE and OV are both set
	- l_mac and l_msb use full 32x32-bit to 64-bit multiply
	- l_mac and l_msb set OV bit if add stage overflows, which may
	cause exception
	- l_mul does not touch CY flag
	- l_div, l_divu now set OV bit for DBZ

* testsuite/ChangeLog:

2013-04-04  Peter Gavin  <pgavin@gmail.com>

	* or1ksim.tests/inst-set-test.exp: update test to match changes in
	new architecture manual (1.0-rev0), such as AESR/AECR support
	* or1ksim.tests/cfg/or1k/inst-set-test-aecsr.cfg: config for
	inst-set-test.exp, with AECSRP bit in CPUCFGR set (new file)
	* or1ksim.tests/cfg/or1knd/inst-set-test-aecsr.cfg: ditto

* testsuite/test-code-or1k/ChangeLog:

2013-04-04  Peter Gavin  <pgavin@gmail.com>

	* inst-set-test/is-add-test.S: update test to match changes in new
	architecture manual (1.0-rev0), such as AESR/AECR support
	* inst-set-test/is-div-test.S: ditto
	* inst-set-test/is-mac-test.S: ditto
	* inst-set-test/is-mul-test.S: ditto
	* inst-set-test/is-sub-test.S: ditto
fix bug causing "<invalid>" instructions in traces on 64-bit systems

* ChangeLog:
2013-04-10  Peter Gavin  <pgavin@gmail.com>

	* cpu/or32/or32.c: (insn_extract) make sure the new extracted bit
	is unsigned, otherwise the result may become negative and will be
	sign-extended when cast to a 64-bit integer.  This fixes the bug
	on 64-bit systems where "<invalid>" would be printed in traces for
	valid instructions
is-div-test.S: remove wrong code introduced in previous patch

* testsuite/test-code-or1k/ChangeLog

2013-04-22  Peter Gavin  <pgavin@gmail.com>

	* inst-set-test/is-div-test.S: remove wrong code introduced in
	previous patch
fix l.div with dividend 0x8000000 and divisor 0xffffffff

* ChangeLog:

2013-04-22  Peter Gavin  <pgavin@gmail.com>

	* cpu/or32/insnset.c: (l_div) check for 0x80000000 / 0xffffffff,
	and treat it like division by zero (set OV flag, do not write to
	destination register).  The C standard specifies that this
	operation is undefined, and will typically raise an exception,
	aborting the simulator, just like divide by zero.  So this change
	not only changes the ISA, but fixes a bug in the simulator.

* testsuite/ChangeLog:

2013-04-22  Peter Gavin  <pgavin@gmail.com>

	* or1ksim.test/inst-set-test.exp: add test case for l.div with
	dividend 0x80000000 and divisor 0xffffffff.  The behavior should
	be the same as for divide by zero (set OV flag, don't write
	result).

* testsuite/test-code-or1k/ChangeLog:

2013-04-22  Peter Gavin  <pgavin@gmail.com>

	* inst-set-test/is-div-test.S: add test case for l.div with
	dividend 0x80000000 and divisor 0xffffffff.  The behavior should
	be the same as for divide by zero (set OV flag, don't write
	result).
add support for atomic operation instructions

This adds support for the atomic load-link/store-conditional
instruction l.lwa and l.swa.
In addition to that, tests that ensure their correct behaviour
are also added.

* ChangeLog:

2014-05-04  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>

	* cpu/common/abstract.c:
	(set_mem32) Clear atomic reserve on write to atomic address.
	(set_mem16) Likewise.
	(set_mem8) Likewise.
	* cpu/common/execute.h <cpu_state>: Add loadlock_active and
	loadlock_address members.
	* cpu/or1k/except.c (except_handle): Clear atomic reserve on
	exceptions.
	* cpu/or32/insnset.c:
	(l_swa): New function.
	(l_lwa): Likewise.
	* cpu/or32/or32.c <or1ksim_or32_opcodes>: Add l.lwa and l.swa
	instructions.
	* cpu/or32/simpl32-defs.h: Add l_swa and l_lwa declarations.
	* cuc/load.c <conv>: Add l.lwa and l.swa instructions.

* testsuite/ChangeLog:

2014-05-04  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>

	* or1ksim.tests/atomic.exp: New file. Test for atomic
	(l.lwa/l.swa) instructions.

* testsuite/test-code-or1k/ChangeLog:

2014-05-04  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>

	* atomic: New directory. Tests for l.lwa and l.swa atomic
 			instructions.
	* atomic/atomic.S: New file.
	* atomic/Makefile.in: Likewise.
	* atomic/Makefile.am: Likewise.
	* Makefile.am: Add atomic test.
	* configure.ac: Likewise.
	* Makefile.in: Regenerated.
	* configure: Likewise.