vetar: fix build with new hdlmake
lvds: add an extra register stage... just in case
lvds: fix confusion between g_inputs and g_outputs
pexaria5: high-Z is wrong default for LVDS outputs
pexaria5: assign butis C2 and T0 clock to HDMI
build: rerun hdlmake
fpga-config-space: update submodule legacy-vme, compatibility
                   with VHDL 1993
vetar: remove vhdl-2008ism