MIPS64: fr1 mode 1/5: Update sim FP code for fr1.

MIPS cpus (beyond early MIPS-I instruction set) support two FPU
operating modes, as controlled by system software setting the
status register FR bit.

FR=0 mode is still used in the O32 ABI, and is in common use
still. FR=1 mode is used for 64-bit operation on n64 ABI.

This series of CL's changes the code to operate in FR=1 mode,
and does NOT preserve FR=0 compability.

A later CL will allow us to operate in either mode, if we
do intend to support 32 and 64 bit operation from a single
code base.
MIPS64: fr1 mode 2/5: Use real ldc1/sdc1 to load/store doubles.

With FR=1 mode (32 64-bit FP regs), we can no longer use paired
lwc1/swc1 to load/store doubles, since we are not using reg pairs
like f0, f1. In FR=1 mode, both f0 and f1 are independent 64-bit
registers.

Note that our reason for using paired lwc1 instructions was to
avoid the need to align all doubles, which is an issue on 32-bit
v8. I believe that all doubles will be correctly aligned in
64-bit v8, but we will have to prove that via the tests.
MIPS64: fr1 mode 3/5: Implement mthc1/mfhc1 and dmtc1/dmfc1 instructions.

In assembler and simulator (already in disasm).

Also fix a couple sim bugs in FP instruction implementation.
MIPS64: fr1 mode 4/5: Fix all the FP cctests to work in fr1 mode.

Also need a change to macro-asm, for some called functions.
MIPS64: fr1 mode 5/5: Convert rest of files to use fr1 mode properly.

This is just converting a few mtc1/mfc1 on odd FP regs to use
mthc1/mfhc1 on the single base FP register. All operations on
FP register-pairs are eliminated.

However, this CL does not change the allocator to start using the
new FP registers. That will come in a later change.

This is a hard-conversion to FR1 mode. To later combine this port with
mips32 will require macro-wrapping these to support either mode. At that
time we will also have to support mips32r1 cpus which do not have these
instructions.