sunxi-mmc: Make mmc mod clk div pll clk freq independent

Change how we calculate the mod clk div so that it will work for a pll clk
of 600 or 1200 too.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi: Enable pll6 by default on all models

So that we can use it as a clocksource for modules, ie for mmc. This
allows discoupling the actual mmc clock rate we get from the ram speed,
and will lead to getting exact clockspeeds for mmc rather then something
approximately right.

As an added bonus this makes things easier on sun6i since pll5 cannot be
used as a module source at all there.

This has been tested on sun4i, sun5i and sun7i.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi-mmc: Use pll6 as clock source

This discouples the actual mmc clock rate we get from the ram speed,
which leads to getting exact clockspeeds for mmc rather then something
approximately right.

As an added bonus this makes things easier on sun6i since pll5 cannot be
used as a module source at all there.

This has been tested on sun4i, sun5i and sun7i.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi-mmc: Simplify data_buf1_sz calculations

Since SDXC_DES_BUFFER_MAX_LEN is always a power of 2,
"(SDXC_DES_BUFFER_MAX_LEN - 1) & SDXC_DES_BUFFER_MAX_LEN" is just a really
complicated way of writing 0.

Since writing 0 to data_buf1_sz means transfer SDXC_DES_BUFFER_MAX_LEN bytes,
there is no need to set remain to SDXC_DES_BUFFER_MAX_LEN when it is 0.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>