alu: add alternative non-stall "PIPELINED" mul impementation

The "PIPELINED" mul implementation is similar to the
"THREESTAGE" implementation, but with the difference that
instead of stalling the pipeline while the multiply is performed
in execute stage, the pipelining of the multiply go 'along' with
the cpu pipeline.
I.e. the multiply operation will be finished in write-back stage,
and the result muxed directly into the register-file.

This comes with the following implications:
The two following instructions after the multiply
instruction can't have their input forwarded from
execute stage nor ctrl/mem stage. Instead, nop-bubbles
are inserted on such occations.

Since the result is not ready in execute stage,
generating multiply overflows becomes cumbersome and
has therefore been omitted.

While this gives a significant boost in multiply operations,
a multiply now takes (best case) 1 cycle instead of 3
(and coremark score sees about a 4% boost),
timing reports show worse timing score with this implementation.
However the worst critical paths looks unrelated to the
multiplier, so some further work here is needed.

On the other hand, comparing resource usage between the
"PIPELINED" and "THREESTAGE" implementations,
the "PIPELINED" takes less resources.