Fix a bug about generating undef operand when optimising shuffle vector and insert element in instruction combine.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198730 91177308-0d34-0410-b5e6-96231b3b80d8
llvm-readobj: add support for ARM EHABI unwind info

This adds some preliminary support for decoding ARM EHABI unwinding information.
The major functionality that remains from complete support is bytecode
translation.

Each Unwind Index Table is printed out as a separate entity along with its
section index, name, offset, and entries.

Each entry lists the function address, and if possible, the name, of the
function to which it corresponds.  The encoding model, personality routine or
index, and byte code is also listed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198734 91177308-0d34-0410-b5e6-96231b3b80d8
ARM IAS: properly handle expression operands

Operands which involved label arithemetic would previously fail to parse.  This
corrects that by adding the additional case for the shift operand validation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198735 91177308-0d34-0410-b5e6-96231b3b80d8
tests: disable ARM unwinding tests if ARM is unavailable

Appease the buildbots for targets which do not build the ARM support by moving
the ARM specific test into a subdirectory and use the lit configuration to
disable them appropriately.

Thanks to chapuni and thakis for explaining how to do this!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198736 91177308-0d34-0410-b5e6-96231b3b80d8