Update HDL and improve UART speed.

This updates the HDL and improves the UART speed significantly.
Rebuild application every time.
Added simulation model and compile script.
Fixed transmit timing out.
Fixed up reception and transmission.
Add signal mux.

Now muxing between internal signal generator and LMS6002D receiver.
Fixed up wrong default value for LMS.
Bump the firmware revision.
Bump version and remove FPGA fixup.
Selectively enable RF module.
More tweaks.  Still times out.
Reset.
More debugging and moving strobes around.
Updating to fix a PIB problem.
hdl: Adding IQ correction files.
Modified stuffs.
add nios control of correction parameters
usb needs to be updated
i2c fixe-up to deal with a name conflict
Fixed minor issues.

ARST_LVL was inadvertantly changed to be a '0' instead of a '1' during the renaming of oc_i2c_master to bladerf_oc_i2c_master.  This is moved back.

Updated to using Quartus II 13.1, and with that discovered that Qsys now outputs '1' or '0' into a Verilog file which should be 1'b0 or 1'b1, so now there is a small sed replacement after generating the Qsys components to handle this problem.