sb-fx6: pca953x: enable DVI transmitter

Enable DVI transmitter by default.
In the past, DVI transmitter has been enabled accidentally, due to
pca953x eGPIO default state (input with a pull-up resistor).

Additionally, set a few more eGPIO(s).

Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
ARM: i.MX6: cm-fx6: ADS7846: change calibration

As ADS7846 uses 12-bit ADC, the existing calibration is
obviously wrong.

Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
touchscreen: ads7846: fix bug in axes inversion

Since it is possible to reconfigure input device driver online,
axes inversion offset cannot be assumed constant for the whole
lifetime.

Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
touchscreen: ads7846: enforce ADC output width

Enforce ADC output is 12 bits width.
For no clear reason, on i.MX6-based CM-FX6, we have experienced a
13-th bit.

Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
mtd: m25p80: add support for m25px16

Although the m25px16 spi flash chip is JEDEC complient and can be used
with the m25p80 driver, the support for it was missing.
Add support for the m25px16 spi flash chip.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
ARM: i.MX6: prevent double regulators init

The function mx6_cpu_regulator_init() is called from both the
mxc_cpufreq_driver_init() function and the cm_fx6_init().
As a result, the cpufreq driver failes to scale the voltage and we have
multiple messages in kernel log:
COULD NOT SET GP VOLTAGE!!!!
COULD NOT SET SOC VOLTAGE BACK!!!!

Prevent this by restricting the mx6_cpu_regulator_init() call to only
one time.
Currently, there is a common way to solve the problem and remove the
call to mx6_cpu_regulator_init() from the board specific function, but
leave it in the mxc_cpufreq_driver_init().

We are not sure that the common way is the best one as we'd like to see
those regulators initialized as soon as possible in the boot process.
So calling the mx6_cpu_regulator_init() from cm_fx6_init() is much
earlier than doing it from mxc_cpufreq_driver_init() as it is a
module_init() call.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
ARM: i.MX6: cm-fx6: CPU regulator init from board file

Call mx6_cpu_regulator_init() from the board file.
This commit effectively reverts commit by Robin Gong of Freescale
"ENGR00234411-1 Sabreauto: fix error print COULD NOT SET GP VOLTAGE".
Double regulators initialization, that the commit above meant to
prevent, is prevented by our commit
"ARM: i.MX6: prevent double regulators init".

Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
ARM: i.MX6: cm-fx6: fix rare cpu stalls

In certain environments (close to temperature operating boundaries)
the i.MX6 SoC has been found to stall.
To fix the problem, the voltage scaling operating points are adjusted
and the minimum voltage for cpu (core) regulator is set to 1.25V.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
ARM: i.MX6: cm-fx6: delete irrelevant comment

Delete irrelevant comment inherited from ARM2 board in the initial
porting time.

Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
Improve CEC driver to support libCEC
cf http://stephan-rafin.net/blog/2013/09/30/i-mx6-cec/ for details

Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
ENGR00295714: GPT Status register bits are cleared inadvertently

GPT Status register bit should be cleared by writing 1.
We do not need to read, modify, write for modifying the bits.
In Linux-3.0.35, while clearing ROV bit we inadvertently clear
other bit causing timer issues.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
Revert "ENGR00223349-4 gpmi: enable the EDO support for mx6q"

This reverts commit 5ca7cbf0a550dd2c0facd674fc27e4ff5232d738.

Although the above commit claims to improve the NAND performance
dramatically, it introduces a regression in supported NAND flash chips.
So for example Hynix H27U1G8F2BTR fails to switch to EDO mode 4 and the
driver aborts. After reverting the above commit, Hynix chip works fine.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
mtd: gpmi: fix kernel BUG due to racing DMA operations

[1] The gpmi uses the nand_command_lp to issue the commands to NAND chips.
    The gpmi issues a DMA operation with gpmi_cmd_ctrl when it handles
    a NAND_CMD_NONE control command. So when we read a page(NAND_CMD_READ0)
    from the NAND, we may send two DMA operations back-to-back.

    If we do not serialize the two DMA operations, we will meet a bug when

    1.1) we enable CONFIG_DMA_API_DEBUG, CONFIG_DMADEVICES_DEBUG,
         and CONFIG_DEBUG_SG.

    1.2) Use the following commands in an UART console and a SSH console:
         cmd 1: while true;do dd if=/dev/mtd0 of=/dev/null;done
         cmd 1: while true;do dd if=/dev/mmcblk0 of=/dev/null;done

    The kernel log shows below:
    -----------------------------------------------------------------
    kernel BUG at lib/scatterlist.c:28!
    Unable to handle kernel NULL pointer dereference at virtual address 00000000
      .........................
    [<80044a0c>] (__bug+0x18/0x24) from [<80249b74>] (sg_next+0x48/0x4c)
    [<80249b74>] (sg_next+0x48/0x4c) from [<80255398>] (debug_dma_unmap_sg+0x170/0x1a4)
    [<80255398>] (debug_dma_unmap_sg+0x170/0x1a4) from [<8004af58>] (dma_unmap_sg+0x14/0x6c)
    [<8004af58>] (dma_unmap_sg+0x14/0x6c) from [<8027e594>] (mxs_dma_tasklet+0x18/0x1c)
    [<8027e594>] (mxs_dma_tasklet+0x18/0x1c) from [<8007d444>] (tasklet_action+0x114/0x164)
    -----------------------------------------------------------------

    1.3) Assume the two DMA operations is X (first) and Y (second).

         The root cause of the bug:
	   Assume process P issues DMA X, and sleep on the completion
	 @this->dma_done. X's tasklet callback is dma_irq_callback. It firstly
	 wake up the process sleeping on the completion @this->dma_done,
	 and then trid to unmap the scatterlist S. The waked process P will
	 issue Y in another ARM core. Y initializes S->sg_magic to zero
	 with sg_init_one(), while dma_irq_callback is unmapping S at the same
	 time.

	 See the diagram:

                   ARM core 0              |         ARM core 1
	 -------------------------------------------------------------
         (P issues DMA X, then sleep)  --> |
                                           |
         (X's tasklet wakes P)         --> |
                                           |
                                           | <-- (P begin to issue DMA Y)
                                           |
         (X's tasklet unmap the            |
      scatterlist S with dma_unmap_sg) --> | <-- (Y calls sg_init_one() to init
                                           |      scatterlist S)
                                           |

[2] This patch serialize both the X and Y in the following way:
     Unmap the DMA scatterlist S firstly, and wake up the process at the end
     of the DMA callback, in such a way, Y will be executed after X.

     After this patch:

                   ARM core 0              |         ARM core 1
	 -------------------------------------------------------------
         (P issues DMA X, then sleep)  --> |
                                           |
         (X's tasklet unmap the            |
      scatterlist S with dma_unmap_sg) --> |
                                           |
         (X's tasklet wakes P)         --> |
                                           |
                                           | <-- (P begin to issue DMA Y)
                                           |
                                           | <-- (Y calls sg_init_one() to init
                                           |     scatterlist S)
                                           |

Cc: stable@vger.kernel.org # 3.2
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
ARM: i.MX6: cm-fx6: disable v4l

Do not call imx6q_add_v4l2_output().
V4l code will be refactored and reintroduced.

Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
ARM: i.MX6: cm-fx6: add v4l init call

Add v4l init call, required, e.g, for XBMC support.
Calls v4l init and reserves dma memory for it.

Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
ARM: i.MX6: cm-fx6: refactor v4l init code

- rename init function cm_fx6_init_v4l_init() to cm_fx6_init_v4l()
- add error handling
- add a comment that explains why the function called in late_init

Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
ARM: i.MX6: cm-fx6: add v4l msize parameter

Add "cm_fx6_v4l_msize" kernel command line parameter
that allows changing the default v4l msize for the dma
coherent memory declaration.

Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
ARM: i.MX6: cm-fx6: clean up cm_fx6_init_v4l()

Clean up cm_fx6_init_v4l() function:
* declare variables in the beginning of the function
* do not check the return value of memblock_alloc_base() which does not
  return in case of error (panic)
* check return value of memblock_remove() and propagate the error
* IS_ERR() is not suitable as return value, use PRT_ERR() instead
* check return value of dma_declare_coherent_memory() function

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
MXC V4L2 Capture: Stop driver from sending infinite standard enumeration responses.

Stop driver from sending infinite standard enumeration responses.
This should allow v4l2src to proceed.

Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>
ARM: i.MX6: cm-fx6: restrict v4l output for Q/DL SoC

Restrict v4l output for Q/DL SoC.
This limitation solves the sporadic crashes issue on solo lite SoC.

Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
Signed-off-by: Andrey Gelman <andrey.gelman@compulab.co.il>