Makefile: build with newer linaro 4.9.1-2014-06 by Christopher83 and use O3
ARM: dts: msm: add perf-events support for msm8226

Add the device definitions for the Cortex-A7
PMU on msm8226.

Change-Id: I8752ec03ddc3d6d21bf1b996e81eaca7fb57d8b4
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Perf: Fix counts across power collapse

After entry and exit from power collapse, the perf pm_notifier was
calling perf_pmu_disable/enable functions from perf core. Perf core
maintains a counter that it uses to match disable and enable calls but
since pm_notifier is invoked asynchronously, the counter was getting a
non-zero value which prevented the pmu from being enabled. As a result of
this, we were seeing zero counts for some cores across power collapse.

Make the architecture specific calls directly from pm_notifier.

Change-Id: I744e190906a20e70e1e4798235215c385018b121
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
ARM: dts: msm: add perf-events support for msm8x10, msm8x12

Add the device definitions for the Cortex-A7
PMU on msm8x10.

Change-Id: I0e45c01cec2c92e437cc11cee88777bca271b839
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Perf: Make per-process counters configurable

Add feature to enable/disable per-process tracecounters at run-time.

Change-Id: Id6a4c7a0ecd1f5add85464c6ed260860e15c4e3b
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
msm: perf: Add L2 support for tracecounters

Add L2 counter output to the tracecounters implementation.
This enables collection of L2 PMU counter values upon context switch.
Set up filtering based on number of L2 counters and number of cores.
Read L2 counter values and display them along with L1 counter values.

Change-Id: I8bbbd251ee52c66505d22ccf037c601013a916f0
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
Perf: keep events across hotplug

Keep event list alive across a CPU hotplug so that perf
can resume when the CPU comes back online. Bring a CPU
online when exiting a perf session so it can be cleaned
up properly.

Change-Id: Ie0e4a43f751beb77afdc84e9d52b21780f279d80
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Perf: bring CPU online if needed when disabling irq

When disabling an irq, check that the CPU is online
before trying to run on that CPU. Bring the CPU
online if necessary.

This fixes a problem where a CPU that was not online
when disabling the irq caused the disable and the
free to fail. A subsequent attempt to request the irq
also failed because it had not been freed.

Change-Id: Ib873b5ded83ab843ea4e609f196a31ef0083a213
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Perf: Support sw events across hotplug

When CPUs are hotplugged off and on, let the various
sw events continue after the hotplug.

Change-Id: Id1aaf30c459c9cf7c9c38967f9ccad56d4062fd3
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
msm: perf: initialise krait perf L2 counter enables

Clear the L2 counter enables at initialisation.
They are undefined out of reset.

Change-Id: I957106012625ae09efec47d4f657381963d87a5a
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
msm: perf: clean up duplicate constraint events

Events with a duplicate constraint are set to state=OFF when detected,
so that their duplicate counts are not read. However, they were not being
cleaned up because the core code only cleaned up ACTIVE events.
This resulted in counters not being freed and eventually running out
of resources.

Clean up the events with state==OFF that were marked that way because of
constraint duplication.
Ensure counts are not updated for OFF events.

Change-Id: If532801c79e6ad6809869eb0a3063774f00c92c3
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>