Iniciado o Mixer, implementando serializador para CIC
Mixer working in the testbench
Small improvement in the mixer.
Mudancas no mixer
More tests using gencores
Generalized input conditioner
Generic multiplier
Criado dds de frequencia fixa
Generic CIC filter tested and improved
Cordic module added, still lacks proper testing for polar to rect function.
VHDL CORDIC workaround to avoid minor glitch from Verilog version.

It generates a verilog version 1-bit wider so it avoids the region where a wwird glitch happens. Still investigating on the glitch.
Concluido CORDIC, agora com opcao de rotate mode (polar_to_rect
Removed emacs temp files

Conflicts:

	hdl/modules/wb_un_cross/wbgen/wb_bpm_swap_regs.h
	models/blackboxes/lut_sweep.vhd
Atualizado gitignore
Tested divider with 32-bit input and 29-bit precision output

Conflicts:

	hdl/modules/Manifest.py
Removed .dat files and added the ".samples" extension to gitignore.
Better DDS implementation for the mixer

Conflicts:

	hdl/modules/Manifest.py
Mixer corrected and tested
CIC filter tests corrected, filter tested
CIC OBOE corrected